公开(公告)号：US20240363165A1

公开(公告)日：2024-10-31

申请号：US18630482

申请日：2024-04-09

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kento SAKANE ,  Masanori TSUTSUMI ,  Hiroyuki TANAKA ,  Naohiro HOSODA ,  Takumi MORIYAMA

IPC: G11C16/04 ,  H01L23/522 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/30 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: G11C16/0483 ,  H01L23/5226 ,  H01L23/5283 ,  H10B41/10 ,  H10B41/27 ,  H10B41/30 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A memory device includes a first-tier alternating stack of first insulating layers and first electrically conductive layers, a source layer overlying the first-tier alternating stack, a second-tier alternating stack of second insulating layers and second electrically conductive layers overlying the source layer, a memory opening vertically extending through the first-tier alternating stack, the source layer, and the second-tier alternating stack, a memory opening fill structure located in the memory opening and comprising a vertical stack of first memory elements and a vertical semiconductor channel vertically extending through each of the first electrically conductive layers, the source layer, and the second electrically conductive layers, and having a sidewall in contact with the source layer, and a bottom drain region in contact with a bottom portion of the vertical semiconductor channel.

公开(公告)号：US20240260267A1

公开(公告)日：2024-08-01

申请号：US18356919

申请日：2023-07-21

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Masanori TSUTSUMI ,  Naohiro HOSODA ,  Takumi MORIYAMA ,  Ryota SUZUKI ,  Takashi KUDO ,  Nobuyuki FUJIMURA

IPC: H10B43/27 ,  H10B43/35

CPC classification number: H10B43/27 ,  H10B43/35

Abstract: A method of making a memory device includes forming an alternating stack of insulating layers and sacrificial material layers, where a silicon oxycarbide liner is interposed between a first sacrificial material layer and a first insulating layer, and the first sacrificial material layer is direct contact with a second insulating layer or a dielectric material layer composed of a silicon oxide material, forming a memory opening through the alternating stack, forming a memory opening fill structure in the memory opening, forming backside recesses by removing the sacrificial material layers selective to the silicon oxycarbide liner, and forming electrically conductive layers in the backside recesses.

公开(公告)号：US20220216145A1

公开(公告)日：2022-07-07

申请号：US17655827

申请日：2022-03-22

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Masanori TSUTSUMI ,  Naohiro HOSODA ,  Shuichi HAMAGUCHI ,  Kazuki ISOZUMI ,  Genta MIZUNO ,  Yusuke MUKAE ,  Ryo NAKAMURA ,  Yu UEDA

IPC: H01L23/522 ,  H01L23/532 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11519

Abstract: A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings vertically extending through the alternating stack, memory opening fill structures located in the memory openings, where each of the memory opening fill structures contains a memory film and a vertical semiconductor channel that extend vertically, and each memory film includes a crystalline blocking dielectric metal oxide layer, and a metal oxide amorphous dielectric nucleation layer located between each of the vertically neighboring electrically conductive layers and insulating layers, and located between each of the crystalline blocking dielectric metal oxide layers and each of the electrically conductive layers.

公开(公告)号：US20220181343A1

公开(公告)日：2022-06-09

申请号：US17113254

申请日：2020-12-07

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Naohiro HOSODA ,  Masanori TSUTSUMI ,  Kota FUNAYAMA

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L23/522 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11526

Abstract: A memory die includes an alternating stack of insulating layers and electrically conductive layers located between a drain-side dielectric layer and a source-side dielectric layer. Memory openings vertically extend through the alternating stack. Each of the memory openings has a greater lateral dimension an interface with the source-side dielectric layer than at an interface with the drain-side dielectric layer. Memory opening fill structures are located in the memory openings. Each of the memory opening fill structures includes a vertical semiconductor channel, a vertical stack of memory elements, and a drain region. A logic die may be bonded to a source-side dielectric layer side of the memory die.

公开(公告)号：US20240179906A1

公开(公告)日：2024-05-30

申请号：US18352752

申请日：2023-07-14

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Naohiro HOSODA ,  Kazuki ISOZUMI ,  Takayuki MAEKURA ,  Hiroyuki OGAWA ,  Koichi MATSUNO

IPC: H10B43/27

CPC classification number: H10B43/27

Abstract: A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers, memory openings vertically extending through the alternating stack, and memory opening fill structures located in the memory openings and including a respective vertical semiconductor channel and a respective vertical stack of memory cells. An integrated line-and-via structure is provided, which is a unitary structure including a metallic plate portion that is a portion of or laterally contacts an electrically conductive layer, and a metallic via portion that vertically extends through dielectric material plates that overlie the metallic plate portion.

公开(公告)号：US20220270967A1

公开(公告)日：2022-08-25

申请号：US17663055

申请日：2022-05-12

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Naohiro HOSODA ,  Masanori TSUTSUMI

IPC: H01L23/522 ,  H01L23/532 ,  H01L27/11519 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11524

Abstract: A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings vertically extending through the alternating stack, memory opening fill structures located in the memory openings, where each of the memory opening fill structures includes a memory film and a vertical semiconductor channel that extend vertically, and each memory film includes a first metal oxide blocking dielectric layer, and a second metal oxide blocking dielectric layer located between each of the vertically neighboring electrically conductive layers and insulating layers, and located between each of the first metal oxide blocking dielectric layers and each of the electrically conductive layers.

公开(公告)号：US20200258876A1

公开(公告)日：2020-08-13

申请号：US16847857

申请日：2020-04-14

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Naohiro HOSODA ,  Kazuma SHIMAMOTO ,  Tetsuya SHIRASU ,  Yuji FUKANO ,  Akio NISHIDA

IPC: H01L25/18 ,  G11C16/24 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11573 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11565 ,  G11C16/08 ,  H01L27/11529 ,  H01L27/11582 ,  G11C16/26

Abstract: A bonded assembly includes a memory die including a three-dimensional memory array located on a first single crystalline semiconductor substrate, and a logic die including a peripheral circuitry located on a second single crystalline semiconductor substrate and bonded to the memory die. The three-dimensional memory array includes word lines and bit lines. The logic die includes field effect transistors having semiconductor channels configured to flow electrical current along a channel direction that is parallel to the bit lines or word lines. Different crystallographic orientations are used for the first and second single crystalline semiconductor substrates. The crystallographic orientations of the first single crystalline semiconductor substrate are selected to minimize stress deformation of the memory chip, while the crystallographic orientations of the second single crystalline semiconductor substrate are selected to maximize device performance of the peripheral circuitry.

公开(公告)号：US20240213147A1

公开(公告)日：2024-06-27

申请号：US18355067

申请日：2023-07-19

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Naohiro HOSODA ,  Tatsuya HINOUE

IPC: H01L23/522 ,  H01L23/528 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: H01L23/5226 ,  H01L23/5283 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A three-dimensional memory device may be formed by forming a vertically alternating sequence of insulating layers and sacrificial material layers over a substrate, forming memory openings, forming sacrificial memory opening fill structures in the memory openings, forming first cavities by removing a first subset of the sacrificial memory opening fill structures, forming laterally-extending cavities by performing an isotropic etch process that laterally recesses the sacrificial material layers, forming electrically conductive layers in the laterally-extending cavities, forming second cavities by removing the second subset of the sacrificial memory opening fill structures, and forming memory opening fill structures in each of the first cavities and the second cavities.

公开(公告)号：US20190198515A1

公开(公告)日：2019-06-27

申请号：US15850073

申请日：2017-12-21

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Naohiro HOSODA ,  Keisuke SHIGEMURA ,  Junichi ARIYOSHI ,  Kazuki KAJITANI ,  Yuji FUKANO

IPC: H01L27/11556 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/1157 ,  H01L21/265 ,  H01L21/266

CPC classification number: H01L27/11556 ,  H01L21/26513 ,  H01L21/266 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/408

Abstract: A memory device contains a stack of insulating layers and electrically conductive word line layers, at least one first drain select gate electrode located over the stack and extending through a first drain select transistor and a second drain select transistor, at least one second drain select gate electrode located between the first drain select electrode and the stack, and extending through a third drain select transistor and a fourth drain select transistor. The first drain select transistor and the third drain select transistor are located in a first NAND memory string. The second drain select transistor and the fourth drain select transistor are located in a second NAND memory string different from the first NAND memory string. The first drain select transistor has a higher threshold voltage than the second drain select transistor. The third drain select transistor has a lower threshold voltage than the fourth drain select transistor.

公开(公告)号：US20190096808A1

公开(公告)日：2019-03-28

申请号：US15717102

申请日：2017-09-27

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Masanori TSUTSUMI ,  Naohiro HOSODA

IPC: H01L23/535 ,  H01L27/11556 ,  H01L27/11582 ,  H01L21/768

CPC classification number: H01L23/535 ,  H01L21/76895 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582

Abstract: A three-dimensional memory device includes laterally spaced apart vertically alternating stacks of insulating strips and word line electrically conductive strips located over a substrate, memory stack structures extending through the multiple vertically alternating stacks, word line contact via structures contacting a top surface of the respective word line electrically conductive strips, field effect transistors overlying the word line contact via structures, and connector line structures which are electrically connected to respective subsets of the word line electrically conductive strips in different vertically alternating stacks through the field effect transistors.