公开(公告)号：US10672780B1

公开(公告)日：2020-06-02

申请号：US16284240

申请日：2019-02-25

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Takeshi Kawamura ,  Akihisa Sai ,  Naoki Ihata

IPC: H01L27/11556 ,  H01L21/768 ,  H01L23/522 ,  H01L27/11565 ,  H01L27/11582 ,  H01L27/11519 ,  H01L23/528

Abstract: Memory openings and support openings are formed in a memory array region and a staircase region, respectively, through an alternating stack of insulating layers and spacer material layers. Pedestal channel portions and pedestal semiconductor portions are formed at the bottom of the memory openings and the support openings, respectively. Semiconductor oxide plates are provided only in a distal subset of the support openings that are spaced from the memory array region by more than a threshold separation distance. Memory openings are filled with memory opening fill structures, and support openings are filled with support pillar structures. Proximal support pillar structures located adjacent to the memory array region provide internal electrically conductive paths for discharging accumulated electrical charges. During an anisotropic etch process that forms the backside trench, the proximal support pillar structures prevent or reduce deformation of the backside trench, and reduce damage to the memory opening fill structures.