公开(公告)号：US10971514B2

公开(公告)日：2021-04-06

申请号：US16276996

申请日：2019-02-15

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yoshitaka Otsu ,  Kei Nozawa ,  Yashushi Doda ,  Naoto Hojo ,  Yoshinobu Tanaka ,  Koichi Ito ,  Zhiwei Chen ,  Yusuke Ikawa ,  Takeshi Kawamura ,  Ryoichi Ehara

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L23/522 ,  H01L21/311 ,  H01L21/28 ,  H01L21/768 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526

Abstract: A multi-tier three-dimensional memory array includes multiple alternating stacks of insulating layers and electrically conductive layers that are vertically stacked. Memory stack structures including memory films and semiconductor channels extend through the alternating stacks. The alternating stacks are formed as alternating stacks of insulating layers and sacrificial material layers, and are subsequently modified by replacing the sacrificial material layers with electrically conductive layers. Structural support during replacement of the sacrificial material layers with the electrically conductive layers is provided by the memory stack structures and dielectric support pillar structures. The dielectric support pillar structures may be formed only for a first-tier structure including a first-tier alternating stack of first insulating layers and first spacer material layers, or may vertically extend over multiple tiers. The dielectric support pillar structures may be formed before or after formation of stepped surfaces in the alternating stack.

公开(公告)号：US09978766B1

公开(公告)日：2018-05-22

申请号：US15347101

申请日：2016-11-09

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Naohiro Hosoda ,  Takeshi Kawamura ,  Yoko Furihata ,  Kota Funayama

IPC: H01L29/76 ,  H01L27/11556 ,  H01L27/11517 ,  H01L27/11565 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11582

CPC classification number: H01L27/11556 ,  H01L27/11517 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582

Abstract: A first tier structure including a first alternating stack of first insulating layers and first sacrificial material layers is formed over a substrate. First support openings and first memory openings are formed through the first tier structure. A dielectric material portion providing electrical isolation from the substrate is formed in each first memory openings. A second tier structure including a second alternating stack of second insulating layers and second sacrificial material layers is formed the first tier structure. Second support openings and second memory openings are formed through the second tier structure above the first support openings and the first memory openings. Memory stack structures are formed in inter-tier openings formed by adjoining the first and second memory openings. The dielectric material portions provide electrical isolation between the substrate and the vertical semiconductor layers formed within support pillar structures to prevent or reduce electrical shorts to the substrate through the support pillar structures.

公开(公告)号：US09754963B1

公开(公告)日：2017-09-05

申请号：US15243260

申请日：2016-08-22

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Takeshi Kawamura ,  Kota Funayama

IPC: H01L29/76 ,  H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/105

CPC classification number: H01L27/11582 ,  H01L27/11519 ,  H01L27/11531 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11575

Abstract: A first tier structure including a first alternating stack of first insulating layers and first sacrificial material layers is formed over a substrate. First support pillar structures are formed through the first tier structure. A second tier structure including a second alternating stack of second insulating layers and second sacrificial material layers is formed over the first tier structure. Memory stack structures and second support pillar structures are formed through the second tier structure. The first and second sacrificial material layers are replaced with first and second electrically conductive layers while the first support pillar structures, the second support pillar structures, and the memory stack structures provide structural support to the first and second insulating layers. By limiting the spatial extent of the first support pillar structures within the first tier structure, electrical short to backside contact via structures can be reduced.

公开(公告)号：US09728547B1

公开(公告)日：2017-08-08

申请号：US15159034

申请日：2016-05-19

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Shingo Ohsaki ,  Hiroshi Kariya ,  Takuro Maede ,  Takeshi Kawamura

IPC: H01L29/792 ,  H01L27/11556 ,  H01L21/02 ,  H01L21/311 ,  H01L21/768 ,  H01L27/11582 ,  H01L21/3213 ,  H01L27/11563 ,  H01L27/11578 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11519

CPC classification number: H01L27/1157 ,  H01L21/02178 ,  H01L21/02227 ,  H01L21/0228 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/76805 ,  H01L21/76831 ,  H01L27/11563 ,  H01L27/11578 ,  H01L27/11582 ,  H01L28/00

Abstract: Unwanted erosion of dielectric materials around a backside contact trench can be avoided or minimized employing an aluminum oxide liner. An aluminum oxide liner can be formed inside an insulating material layer in a backside contact trench to prevent collateral etching of the insulating material at an upper portion of the backside contact trench during an anisotropic etch that forms an insulating spacer. Alternatively, an aluminum oxide layer can be employed as a backside blocking dielectric layer. An upper portion of the aluminum oxide layer can be converted into an aluminum compound layer including aluminum and a non-metallic element other than oxygen at an upper portion of the trench, and can be employed as a protective layer during formation of a backside contact structure.

公开(公告)号：US09613971B2

公开(公告)日：2017-04-04

申请号：US14808475

申请日：2015-07-24

Applicant: SanDisk Technologies LLC

Inventor： Masahiro Yaegashi ,  Kota Funayama ,  Takeshi Kawamura ,  Dai Iwata

IPC: H01L27/11 ,  H01L27/11524 ,  H01L29/49 ,  H01L29/40 ,  H01L21/265 ,  H01L21/28 ,  H01L29/788 ,  H01L29/167 ,  H01L21/768 ,  H01L21/02 ,  H01L23/528

CPC classification number: H01L27/11524 ,  H01L21/02148 ,  H01L21/02164 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/28273 ,  H01L21/768 ,  H01L23/528 ,  H01L29/167 ,  H01L29/401 ,  H01L29/495 ,  H01L29/7883

Abstract: A NAND flash memory array includes a select line having a first edge region containing a first portion of floating gate material and a second edge region containing a second portion of floating gate material, and having a central region between the first edge region and the second edge region where no floating gate material is present.

公开(公告)号：US10672780B1

公开(公告)日：2020-06-02

申请号：US16284240

申请日：2019-02-25

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Takeshi Kawamura ,  Akihisa Sai ,  Naoki Ihata

IPC: H01L27/11556 ,  H01L21/768 ,  H01L23/522 ,  H01L27/11565 ,  H01L27/11582 ,  H01L27/11519 ,  H01L23/528

Abstract: Memory openings and support openings are formed in a memory array region and a staircase region, respectively, through an alternating stack of insulating layers and spacer material layers. Pedestal channel portions and pedestal semiconductor portions are formed at the bottom of the memory openings and the support openings, respectively. Semiconductor oxide plates are provided only in a distal subset of the support openings that are spaced from the memory array region by more than a threshold separation distance. Memory openings are filled with memory opening fill structures, and support openings are filled with support pillar structures. Proximal support pillar structures located adjacent to the memory array region provide internal electrically conductive paths for discharging accumulated electrical charges. During an anisotropic etch process that forms the backside trench, the proximal support pillar structures prevent or reduce deformation of the backside trench, and reduce damage to the memory opening fill structures.