公开(公告)号：US20210313281A1

公开(公告)日：2021-10-07

申请号：US16838320

申请日：2020-04-02

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Michimoto KAMINAGA ,  Takahiro TANAMACHI ,  Shuya HATAO ,  Hidetoshi NAKAMOTO

IPC: H01L23/58 ,  H01L23/532 ,  H01L27/11556 ,  H01L27/11582

Abstract: A semiconductor die includes semiconductor devices located over a substrate, at least one dielectric material portion that laterally surrounds the semiconductor devices, and interconnect-level dielectric material layers. At least one edge seal ring structure can be provided, each including a composite edge seal via structure and a set of metal barrier structures. The composite edge seal via structure includes a metallic material layer and a dielectric fill material portion. Alternatively or additionally, at least one slit ring structure can laterally surround the semiconductor devices and the metal interconnect structures. Each slit ring structure continuously extends through each of the interconnect-level dielectric material layers and into the at least one dielectric material portion, and includes at least one dielectric material.

公开(公告)号：US20210313240A1

公开(公告)日：2021-10-07

申请号：US16838283

申请日：2020-04-02

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Takahiro TANAMACHI ,  Shuya HATAO ,  Hidetoshi NAKAMOTO ,  Michimoto KAMINAGA

IPC: H01L23/10 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/532 ,  H01L23/522 ,  H01L23/528

Abstract: A semiconductor die includes semiconductor devices located over a substrate, at least one dielectric material portion that laterally surrounds the semiconductor devices, and interconnect-level dielectric material layers. At least one edge seal ring structure can be provided, each including a composite edge seal via structure and a set of metal barrier structures. The composite edge seal via structure includes a metallic material layer and a dielectric fill material portion. Alternatively or additionally, at least one slit ring structure can laterally surround the semiconductor devices and the metal interconnect structures. Each slit ring structure continuously extends through each of the interconnect-level dielectric material layers and into the at least one dielectric material portion, and includes at least one dielectric material.

公开(公告)号：US20210313246A1

公开(公告)日：2021-10-07

申请号：US17062765

申请日：2020-10-05

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Toshiaki MATSUMURA ,  Nao NAGASE ,  Yoshihiko SAITO ,  Nobutoshi SUGAWARA ,  Takahiro TANAMACHI

IPC: H01L23/31 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11519 ,  H01L27/11565 ,  H01L23/522 ,  H01L21/56

Abstract: Semiconductor devices laterally surrounded by at least one dielectric material portion are formed over a substrate. At least one edge seal ring structure is formed around the semiconductor devices and the at least one dielectric material portion. One or more of the at least one edge seal ring structure has a horizontal cross-sectional profile that includes laterally-extending regions that extend laterally with a uniform width between an inner sidewall and an outer sidewall, and notch regions connecting neighboring pairs of the laterally-extending regions and having a greater width than the uniform width. Cavities in the laterally-extending regions are connected to cavities in the notch regions to allow outgassing from the material of the at least one edge seal ring structure.