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    THREE-DIMENSIONAL MEMORY DEVICE CONTAINING THROUGH-MEMORY-LEVEL CONTACT VIA STRUCTURES AND METHOD OF MAKING THE SAME
    3.
    发明申请
    THREE-DIMENSIONAL MEMORY DEVICE CONTAINING THROUGH-MEMORY-LEVEL CONTACT VIA STRUCTURES AND METHOD OF MAKING THE SAME 审中-公开

    公开(公告)号：US20200286917A1

    公开(公告)日：2020-09-10

    申请号：US16881353

    申请日：2020-05-22

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Michimoto KAMINAGA ,  Zhixin CUI

    IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11565 ,  H01L21/768 ,  H01L27/11556 ,  H01L23/532 ,  H01L23/522 ,  H01L27/11575

    Abstract: A contact via structure vertically extending through an alternating stack of insulating layers and electrically conductive layers is provided in a staircase region having stepped surfaces. The contact via structure is electrically isolated from each electrically conductive layer of the alternating stack except for an electrically conductive layer that directly underlies a horizontal interface of the stepped surfaces. A laterally-insulated structure includes a conductive via structure having an upper conductive via portion overlying and contacting an annular area of a top surface of one of the electrically conductive layers, a lower conductive via portion having a lesser lateral dimension than the upper conductive via portion and extending through at least a bottommost one of the electrically conductive layers, and an interconnection conductive via portion located between the upper conductive via portion and the lower conductive via portion and contacting a cylindrical sidewall of the one of the electrically conductive layers.

    SEMICONDUCTOR DIE INCLUDING EDGE RING STRUCTURES AND METHODS FOR MAKING THE SAME
    4.
    发明申请
    SEMICONDUCTOR DIE INCLUDING EDGE RING STRUCTURES AND METHODS FOR MAKING THE SAME 有权

    公开(公告)号：US20210313281A1

    公开(公告)日：2021-10-07

    申请号：US16838320

    申请日：2020-04-02

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Michimoto KAMINAGA ,  Takahiro TANAMACHI ,  Shuya HATAO ,  Hidetoshi NAKAMOTO

    IPC: H01L23/58 ,  H01L23/532 ,  H01L27/11556 ,  H01L27/11582

    Abstract: A semiconductor die includes semiconductor devices located over a substrate, at least one dielectric material portion that laterally surrounds the semiconductor devices, and interconnect-level dielectric material layers. At least one edge seal ring structure can be provided, each including a composite edge seal via structure and a set of metal barrier structures. The composite edge seal via structure includes a metallic material layer and a dielectric fill material portion. Alternatively or additionally, at least one slit ring structure can laterally surround the semiconductor devices and the metal interconnect structures. Each slit ring structure continuously extends through each of the interconnect-level dielectric material layers and into the at least one dielectric material portion, and includes at least one dielectric material.

    THREE-DIMENSIONAL MEMORY DEVICE CONTAINING THROUGH-MEMORY-LEVEL CONTACT VIA STRUCTURES AND METHOD OF MAKING THE SAME
    5.
    发明申请
    THREE-DIMENSIONAL MEMORY DEVICE CONTAINING THROUGH-MEMORY-LEVEL CONTACT VIA STRUCTURES AND METHOD OF MAKING THE SAME 审中-公开

    公开(公告)号：US20200035694A1

    公开(公告)日：2020-01-30

    申请号：US16589337

    申请日：2019-10-01

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Michimoto KAMINAGA

    IPC: H01L27/11521 ,  H01L27/06 ,  H01L27/11578 ,  H01L27/11556 ,  H01L21/768 ,  H01L21/306

    Abstract: A first alternating stack of first insulating layers and first sacrificial material layers with first stepped surfaces is formed over a substrate. A first retro-stepped dielectric material portion is formed on the first stepped surfaces. A second alternating stack of second insulating layers and second sacrificial material layers with second stepped surfaces is formed over the first alternating stack. A second retro-stepped dielectric material portion is formed on the second stepped surfaces. A first conductive via structure is formed through the second retro-stepped dielectric material portion, a bottommost insulating layer of the second alternating stack, and the first retro-stepped dielectric material portion. The sacrificial material layers are replaced with electrically conductive layers. The first conductive via structure is electrically connected to a first electrically conductive layer that replaces a first sacrificial material layer, and is electrically isolated from each second electrically conductive layer in the second alternating stack.

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