公开(公告)号：US20240072142A1

公开(公告)日：2024-02-29

申请号：US18218751

申请日：2023-07-06

Applicant: SEMES CO., LTD.

Inventor： Thomas Jongwan KWON ,  Hae-won CHOI ,  Yunsang KIM

IPC: H01L29/423 ,  H01L21/3213

CPC classification number: H01L29/4236 ,  H01L21/32137

Abstract: Provided is a method of manufacturing a semiconductor device, the method including steps of providing a semiconductor substrate having one or more trenches, forming a gate insulating layer on the semiconductor substrate inside the trenches, and forming a buried gate electrode layer on the gate insulating layer to at least partially fill the trenches, wherein the step of forming the buried gate electrode layer includes a step of repeating a unit cycle a plurality of times, the unit cycle including an atomic layer deposition (ALD) process for forming a conductive layer on the gate insulating layer to serve as the buried gate electrode layer, and an atomic layer etching (ALE) process for preferentially etching portions of the conductive layer formed near the trenches and portions of the conductive layer formed on upper ends of the trenches over other portions of the conductive layer inside the trenches.