OXIDATION AND CORROSION PREVENTION IN SEMICONDUCTOR DEVICES AND SEMICONDUCTOR DEVICE ASSEMBLIES

    公开(公告)号:US20240387425A1

    公开(公告)日:2024-11-21

    申请号:US18787369

    申请日:2024-07-29

    Abstract: In some aspects, the techniques described herein relate to an electronic device including: a substrate; a metallization layer, the metallization layer having: a first surface disposed on the substrate; a second surface opposite the first surface; and a corrosion-prevention implant layer disposed in the metallization layer, the corrosion-prevention implant layer extending from the second surface to a depth from the second surface in the metallization layer, the depth being less than a thickness of the metallization layer; and an electrical connector coupled with the second surface.

    OXIDATION AND CORROSION PREVENTION IN SEMICONDUCTOR DEVICES AND SEMICONDUCTOR DEVICE ASSEMBLIES

    公开(公告)号:US20220328434A1

    公开(公告)日:2022-10-13

    申请号:US17658232

    申请日:2022-04-06

    Abstract: In some aspects, the techniques described herein relate to an electronic device including: a substrate; a metallization layer, the metallization layer having: a first surface disposed on the substrate; a second surface opposite the first surface; and a corrosion-prevention implant layer disposed in the metallization layer, the corrosion-prevention implant layer extending from the second surface to a depth from the second surface in the metallization layer, the depth being less than a thickness of the metallization layer; and an electrical connector coupled with the second surface.

    STRUCTURE AND METHOD FOR ELECTRONIC DIE SINGULATION USING ALIGNMENT STRUCTURES AND MULTI-STEP SINGULATION

    公开(公告)号:US20210296176A1

    公开(公告)日:2021-09-23

    申请号:US17248514

    申请日:2021-01-28

    Abstract: A method for singulating a semiconductor wafer includes providing the semiconductor wafer having a plurality of semiconductor devices adjacent to a first surface, the plurality of semiconductor devices separated by spaces corresponding to where singulation lines will be formed. The method includes providing an alignment structure adjacent to the first surface and providing a material on a second surface of the semiconductor wafer, wherein the material is absent on the second surface directly below the alignment structure. The method includes passing an IR signal through the semiconductor wafer from the second surface to the first surface where the material is absent to detect the alignment structure and align a singulation device to the spaces where the singulation lines on will be formed. The method includes using the singulation device to remove portions of the layer of material aligned to the singulation lines and thereafter plasma etching the semiconductor wafer from the first surface to the second surface through the spaces to form the singulation lines thereby singulating the semiconductor wafer.

Patent Agency Ranking