公开(公告)号：US20240395925A1

公开(公告)日：2024-11-28

申请号：US18796083

申请日：2024-08-06

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Gordon M. GRIVNA

IPC: H01L29/78 ,  H01L21/3065 ,  H01L21/78 ,  H01L23/48 ,  H01L29/06

Abstract: A semiconductor device includes a region of semiconductor material having a first side and a second side opposite to the first side. Active device structures are adjacent to the first side, the active device structures comprising source regions and gate electrodes. A first gate conductor is at the first side electrically connected to the gate electrodes, a drain region is at the second side, a second gate conductor is at the second side, and through-semiconductor vias extending from the first side towards the side and electrically connecting the first gate electrode to the second gate electrode. A source electrode is at the first side electrically connected to the source regions, and a drain electrode is at the second side electrically connected to the drain region. The through-semiconductor vias are electrically isolated from the source regions and the drain region. The structure provides a gate/drain up with a source-down configuration.

公开(公告)号：US20240055298A1

公开(公告)日：2024-02-15

申请号：US18490923

申请日：2023-10-20

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： JeongPyo HONG ,  Mohd Akbar MD SUM ,  Gordon M. GRIVNA

IPC: H01L21/78 ,  H01L21/67 ,  H01L21/3065 ,  H01L23/00

CPC classification number: H01L21/78 ,  H01L21/67069 ,  H01L21/3065 ,  H01L23/564

Abstract: Described implementations include a contaminant-free plasma singulation process, in which residues of materials used during plasma singulation are fully removed from sidewalls of a resulting semiconductor die, without damaging the semiconductor die. From such a contaminant-free plasma singulation process, a semiconductor die may be manufactured. The semiconductor die may include a first plurality of sidewall recesses formed in a sidewall of a substrate of the semiconductor die between a first surface and a second surface of the substrate, each having at most a first depth, as well as a second plurality of sidewall recesses formed in the sidewall of the substrate and disposed between the first plurality of sidewall recesses and the second surface, each having at least a second depth that is greater than the first depth.

公开(公告)号：US20230253468A1

公开(公告)日：2023-08-10

申请号：US17650456

申请日：2022-02-09

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Zia HOSSAIN ,  Balaji PADMANABHAN ,  Christopher Lawrence REXER ,  Gordon M. GRIVNA ,  Sauvik CHOWDHURY

IPC: H01L29/423 ,  H01L29/78 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L29/4236 ,  H01L29/7813 ,  H01L29/7811 ,  H01L29/408 ,  H01L29/66734

Abstract: In one general aspect, an apparatus can include a substrate having a semiconductor region, and a trench defined in the semiconductor region and having a sidewall. The apparatus can include a shield electrode disposed in the trench and insulated from the sidewall of the trench by a shield dielectric, the shield dielectric having a low-k dielectric portion and a high-k dielectric portion. The apparatus can include a gate electrode disposed in the trench and at least partially surrounded by a gate dielectric, and an inter-electrode dielectric disposed between the shield electrode and the gate electrode.

公开(公告)号：US20220277999A1

公开(公告)日：2022-09-01

申请号：US17663863

申请日：2022-05-18

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Gordon M. GRIVNA

IPC: H01L21/78 ,  H01L23/00 ,  H01L29/66 ,  H01L29/778

Abstract: A process can be used to allow processing of thin layers of a workpiece including dies. The workpiece can include a base substrate and a plurality of layers overlying the base substrate. The process can include forming a polymer support layer over the plurality of layers; thinning or removing the base substrate within a component region of the workpiece, wherein the component region includes an electronic device; and singulating the workpiece into a plurality of dies after thinning or removing the base substrate. In another aspect, an electronic device can be formed using such process. In an embodiment, the workpiece may have a size corresponding to a semiconductor wafer to allow wafer-level, as opposed to die-level, processing.

公开(公告)号：US20200258739A1

公开(公告)日：2020-08-13

申请号：US16861615

申请日：2020-04-29

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Gordon M. GRIVNA ,  Stephen ST. GERMAIN

IPC: H01L21/02 ,  H01L23/498 ,  H01L23/15 ,  H01L23/14 ,  H01L21/48 ,  H01L23/495 ,  H01L29/20 ,  H01L21/78

Abstract: A first semiconductor substrate contains a first semiconductor material, such as silicon. A second semiconductor substrate containing a second semiconductor material, such as gallium nitride or aluminum gallium nitride, is formed on the first semiconductor substrate. The first semiconductor substrate and second semiconductor substrate are singulated to provide a semiconductor die including a portion of the second semiconductor material supported by a portion of the first semiconductor material. The semiconductor die is disposed over a die attach area of an interconnect structure. The interconnect structure has a conductive layer and optional active region. An underfill material is deposited between the semiconductor die and die attach area of the interconnect structure. The first semiconductor material is removed from the semiconductor die and the interconnect structure is singulated to separate the semiconductor die. The first semiconductor material can be removed post interconnect structure singulation.

公开(公告)号：US20200098857A1

公开(公告)日：2020-03-26

申请号：US16141761

申请日：2018-09-25

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Gary H. LOECHELT ,  Gordon M. GRIVNA ,  Jaegil LEE ,  MinKyung KO ,  Youngchul CHOI

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L21/762 ,  H01L29/66 ,  H01L21/225 ,  H01L21/764 ,  H01L29/78

Abstract: A transistor device includes an n-doped pillar and a p-doped pillar forming a super-junction structure on a substrate. An isolation structure is disposed in a trench between the n-doped pillar and the p-doped pillar, and a source and a gate are disposed on the n-doped pillar. The isolation structure can include an air gap encapsulated in the trench by an oxide plug. The isolation structure can include an epi liner disposed on surfaces of the n-doped pillar and the p-doped pillar.

公开(公告)号：US20190287855A1

公开(公告)日：2019-09-19

申请号：US16433717

申请日：2019-06-06

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Gordon M. GRIVNA ,  Hou Nion CHAN

IPC: H01L21/78 ,  H01L21/324 ,  H01L21/304 ,  H01L21/683

Abstract: A method for processing a semiconductor substrate includes providing the semiconductor substrate having die formed as part of the semiconductor substrate and separated from each other by singulation lines. The semiconductor substrate has first and second opposing major surfaces and contacts disposed over the first major surface. A layer of material is disposed over the second major surface, and the singulation lines extend inward from the first major surface into the semiconductor substrate without extending through the layer of material so that the layer of material is under the singulation lines. The method includes separating the layer of material proximate to the singulation lines by exposing the layer of material to a reduced temperature below about minus 150 degrees Celsius. In some examples, a cryogenic fluid can be to provide the reduced temperature. The method provides a reliable and efficient way to bulk separate at least the layer of material.

公开(公告)号：US20190214301A1

公开(公告)日：2019-07-11

申请号：US16352218

申请日：2019-03-13

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Gordon M. GRIVNA

IPC: H01L21/78 ,  H01L21/67 ,  H01L23/544 ,  H01L21/477 ,  B28D5/00 ,  H01L21/3065 ,  H01L21/683

CPC classification number: H01L21/78 ,  B28D5/0017 ,  H01L21/3065 ,  H01L21/477 ,  H01L21/67092 ,  H01L21/67098 ,  H01L21/67132 ,  H01L21/67144 ,  H01L21/6836 ,  H01L23/544 ,  H01L2221/68327 ,  H01L2223/54453 ,  Y02P80/30 ,  Y10T225/304 ,  Y10T225/379 ,  Y10T225/386

Abstract: A method for forming an electronic device includes providing a wafer having a plurality of die formed as part of the wafer and separated from each other by spaces. A layer of material is disposed atop a major surface of the wafer and the layer of material is placed adjacent to first carrier substrate comprising a first adhesive layer. The wafer is singulated through the spaces to form singulation lines. A second carrier substrate comprising a second adhesive layer is placed onto an opposite major surface of the wafer. The method includes moving a mechanical device adjacent to and in a direction generally parallel to one of the first carrier substrate or the second carrier substrate to separate the layer of material in the singulation lines. In one example, the second adhesive layer has an adhesive strength that is less than that of the first adhesive layer.

公开(公告)号：US20180342423A1

公开(公告)日：2018-11-29

申请号：US15938115

申请日：2018-03-28

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Gordon M. GRIVNA ,  Hou Nion CHAN

IPC: H01L21/78 ,  H01L21/683 ,  H01L21/324

CPC classification number: H01L21/78 ,  H01L21/304 ,  H01L21/324 ,  H01L21/6835 ,  H01L21/6836 ,  H01L2221/68327

Abstract: A method of processing a substrate includes providing a substrate having die formed as part of the substrate and separated from each other by spaces, wherein the substrate has first and second opposing major surfaces, and wherein a layer of material is formed atop the second major surface. The method includes placing the substrate onto a carrier substrate and removing portions of the substrate through the spaces to form gaps between adjoining die. The gaps extend at least partially through the substrate towards the second major surface. The method includes exposing the layer of material to a reduced temperature while the substrate is constrained in a first direction between a plate structure and a support structure, wherein the exposing step expands the gaps between the adjoining die in a second direction to separate at least portions of the layer of material. The method provides a reliable and efficient way to bulk separate at least the layer of material.

公开(公告)号：US20180254217A1

公开(公告)日：2018-09-06

申请号：US15446281

申请日：2017-03-01

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Gordon M. GRIVNA ,  Stephen ST. GERMAIN

IPC: H01L21/78 ,  H01L21/02 ,  H01L21/48 ,  H01L29/20 ,  H01L23/495

CPC classification number: H01L21/7806 ,  H01L21/02381 ,  H01L21/0254 ,  H01L21/4825 ,  H01L21/78 ,  H01L23/49562 ,  H01L29/2003

Abstract: A first semiconductor substrate contains a first semiconductor material, such as silicon. A second semiconductor substrate containing a second semiconductor material, such as gallium nitride or aluminum gallium nitride, is formed on the first semiconductor substrate. The first semiconductor substrate and second semiconductor substrate are singulated to provide a semiconductor die including a portion of the second semiconductor material supported by a portion of the first semiconductor material. The semiconductor die is disposed over a die attach area of an interconnect structure. The interconnect structure has a conductive layer and optional active region. An underfill material is deposited between the semiconductor die and die attach area of the interconnect structure. The first semiconductor material is removed from the semiconductor die and the interconnect structure is singulated to separate the semiconductor die. The first semiconductor material can be removed post interconnect structure singulation.