公开(公告)号：US20240212748A1

公开(公告)日：2024-06-27

申请号：US18233350

申请日：2023-08-14

Applicant: SHANGHAITECH UNIVERSITY

Inventor： Yifei LI ,  Jian CHEN ,  Yajun HA ,  Hongyu CHEN

IPC: G11C11/419

CPC classification number: G11C11/419

Abstract: An ultra-low-voltage static random access memory (SRAM) cell for eliminating half-select-disturbance under a bit interleaving structure includes a cross-coupled inverter pair, two N-type write transistors NM1 and NM2, two P-type write transistors PM1 and PM2, and two N-type transistors NM3 and NM4, where the two N-type transistors NM3 and NM4 form a readout path. The present disclosure can be applied to applications with a storage requirement at an ultra-low voltage, especially applications with certain requirements for an access speed and reliability of an SRAM at a low voltage. Compared with other different SRAM cells, the ultra-low-voltage SRAM cell can achieve higher read and write working frequencies with similar energy consumptions.