公开(公告)号：US20240212748A1

公开(公告)日：2024-06-27

申请号：US18233350

申请日：2023-08-14

Applicant: SHANGHAITECH UNIVERSITY

Inventor： Yifei LI ,  Jian CHEN ,  Yajun HA ,  Hongyu CHEN

IPC: G11C11/419

CPC classification number: G11C11/419

Abstract: An ultra-low-voltage static random access memory (SRAM) cell for eliminating half-select-disturbance under a bit interleaving structure includes a cross-coupled inverter pair, two N-type write transistors NM1 and NM2, two P-type write transistors PM1 and PM2, and two N-type transistors NM3 and NM4, where the two N-type transistors NM3 and NM4 form a readout path. The present disclosure can be applied to applications with a storage requirement at an ultra-low voltage, especially applications with certain requirements for an access speed and reliability of an SRAM at a low voltage. Compared with other different SRAM cells, the ultra-low-voltage SRAM cell can achieve higher read and write working frequencies with similar energy consumptions.

公开(公告)号：US20230197154A1

公开(公告)日：2023-06-22

申请号：US17802968

申请日：2021-09-22

Applicant: SHANGHAITECH UNIVERSITY

Inventor： Jian CHEN ,  Yajun HA

IPC: G11C15/04

CPC classification number: G11C15/04

Abstract: A static random-access memory (SRAM) cell for high-speed content-addressable memory (CAM) and in-memory Boolean logic operations includes a standard 6T-SRAM and two additional PMOS access transistors, where read word lines of the two positive-channel metal oxide semiconductor (PMOS) access transistors P1 and P2 are RWLR and RWLL respectively, and under the control thereof, a differential read port RBL/RBL is formed. The SRAM cell is suitable for multi-row address selection, and typically applied to in-memory high-speed CAM and in-memory Boolean logic operations. Due to PMOS device characteristics, the structure design of the SRAM cell can avoid read disturbance generated by an in-memory SRAM, and ensure that the SRAM can perform in-memory CAM and in-memory Boolean logic operations stably at a high speed. In addition, this SRAM-based IMC solution supports commercial CMOS technology, and has an opportunity to leverage a large number of existing on-chip SRAM caches.