公开(公告)号：US20240281256A1

公开(公告)日：2024-08-22

申请号：US18646818

申请日：2024-04-26

Applicant: SHANGHAITECH UNIVERSITY

Inventor： Yuhan GU ,  Chaolin RAO ,  Minye WU ,  Xin LOU ,  Pingqiang ZHOU ,  Jingyi YU

IPC: G06F9/38 ,  G06T1/20 ,  G06T15/00

CPC classification number: G06F9/3885 ,  G06T1/20 ,  G06T15/005

Abstract: A computing core for rendering an image computing core comprises a position encoding logic and a plurality of pipeline logics connected in series in a pipeline. The position encoding logic is configured to transform coordinates and directions of sampling points corresponding to a portion of the image into high dimensional representations. The plurality of pipeline logics are configured to output, based on the high dimensional representation of the coordinates and the high dimensional representation of the directions, intensity and color values of pixels corresponding to the portion of the image in one pipeline cycle. The plurality of pipeline logics are configured to run in parallel.