公开(公告)号：US11909408B2

公开(公告)日：2024-02-20

申请号：US17907099

申请日：2021-03-24

申请人： SHENZHEN PANGO MICROSYSTEMS CO., LTD.

发明人： Shengwen Xiang ,  Ying Liu

IPC分类号： H03L7/197 ,  G06F1/10

CPC分类号： H03L7/1974 ,  G06F1/10

摘要： A SerDes module clock network architecture comprises, a reference clock input port, a plurality of data transmission channels, several user logic interfaces, several frequency division branches and a phase locked loop. The reference lock input port receives an input clock and conveys the input clock to the phase locked loop, the phase locked loop receives the input lock and outputs a PLL output clock signal, the PLL output clock signal is conveyed to the plurality of data transmission channels, and the PLL output clock signal is conveyed to the frequency division branches, and after frequency division, user interface clocks are output and conveyed to the user logic interfaces. When the PLL output clock signal in a SerDes is provided to an internal dedicated channel, several frequency division branches are also divided, and after frequency division, the signal is output to the user logic interfaces for use by an FPGA.