公开(公告)号：US20200006310A1

公开(公告)日：2020-01-02

申请号：US16465455

申请日：2016-11-30

申请人： SHENZHEN XIUYUAN ELECTRONIC TECHNOLOGY CO., LTD

发明人： Chuan HU ,  Junjun LIU ,  Yuejin GUO ,  Edward Rudolph PRACK

IPC分类号： H01L25/00 ,  H01L25/18 ,  H01L25/16 ,  H01L23/498 ,  H01L21/56 ,  H01L23/31

摘要： An integrated circuit system and a packaging method therefor are disclosed. The method includes providing a first carrier and a second carrier oppositely, with a first device set of the first carrier and a second device set of the second carrier both located between the first and second carriers, providing a molding material between the first and second carriers to make the first and second device sets respectively in contact with the molding material, curing the material to make the first and second device sets respectively mounted at two sides of the molding material, making the first and second carriers detached from the first device set and the molding material and from the second device set and the molding material respectively; and forming connection holes in the molding material and fabricating a conductive layer which extend into the connection holes to electrically connect the first and second device sets.

公开(公告)号：US20190295982A1

公开(公告)日：2019-09-26

申请号：US16465059

申请日：2017-03-13

申请人： SHENZHEN XIUYUAN ELECTRONIC TECHNOLOGY CO., LTD

发明人： Chuan HU ,  Junjun LIU

IPC分类号： H01L23/00 ,  H01L23/498 ,  H01L21/48

摘要： A chip connection method and structure are provided. The method includes: providing a first connection line and a second connection line on a substrate, wherein, in the thickness direction of the substrate, a distance between the first connection line and the chip is smaller than a distance between the second connection line and the chip providing the chip on a top surface of the substrate, the chip being provided with at least two chip pins; and providing the substrate with a second through hole corresponding to the second connecting line, and provided therein with a second conductive layer, at least one chip pin being electrically connected to the first connection line, and at least one of the remaining chip pin being corresponding to a first opening of the second through hole, and the second conductive layer electrically connecting the chip pin and the second connection line.