公开(公告)号：US20250015811A1

公开(公告)日：2025-01-09

申请号：US18746765

申请日：2024-06-18

Applicant: SILEAD INC..

Inventor： Jinling ZHOU ,  Xianyin YU ,  Chenjun WENG

IPC: H03M1/12 ,  H03M1/46

Abstract: An analog-to-digital converter, a touch sensing chip and an electronic device are disclosed. The ADC includes a digital-to-analog conversion circuit, a comparator, a successive approximation register logic circuit and a residue sampling and summing circuit, the successive approximation register logic circuit coupled to output terminal of the comparator and control terminal of the digital-to-analog conversion circuit, the successive approximation register logic circuit configured to produce a corresponding quantized digital signal each time, based on the result of comparison from the comparator, the residue sampling and summing circuit configured to obtain a corresponding residue each time, by sampling residual voltage output from digital-to-analog conversion circuit, sum previous sampled residue and common reference voltage and provide the sum to the comparator, the comparator configured to compare a current output of the residue sampling and summing circuit with a current output of the digital-to-analog conversion circuit and thereby obtain current result of comparison.

公开(公告)号：US20250007533A1

公开(公告)日：2025-01-02

申请号：US18740664

申请日：2024-06-12

Applicant: SILEAD INC.

Inventor： Jinling ZHOU ,  Jun YANG ,  Hongzhen CHEN

IPC: H03M3/00 ,  G06F3/041

Abstract: A touch detection circuit, a touch sensing chip and an electronic device are disclosed. The touch detection circuit includes: a charge/discharge circuit, a 1st-order N-bit ΔΣADC comprising an adder, an integrator, an N-bit ADC and an N-bit DAC, the adder comprising two input terminals coupled respectively to an output terminal of the charge/discharge circuit and an output terminal of the N-bit DAC, the N-bit DAC comprising an input terminal coupled to an output terminal of the N-bit ADC, wherein the integrator is configured to integrate net incoming charge that the integrator receives; the N-bit ADC is configured to quantize an output of the integrator into an N-bit digital signal; the N-bit DAC is configured to provide subtractive reference charge according to the instruction of the N-bit digital signal; and the adder is configured to derive the net incoming charge by subtracting the subtractive reference charge from the sense charge.