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公开(公告)号:US20210043125A1
公开(公告)日:2021-02-11
申请号:US16984633
申请日:2020-08-04
Applicant: SILICON WORKS CO., LTD.
Inventor: Jung Min CHOI , Ju Ho LEE , Jung Hwan CHOI
IPC: G09G3/20
Abstract: An embodiment of the present disclosure relates to a display device allowing minimizing repetitive transmissions and receptions of identical pieces of image data so as to reduce power consumption due to the repetitive transmissions and receptions of identical pieces of image data.
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公开(公告)号:US20190043409A1
公开(公告)日:2019-02-07
申请号:US16051860
申请日:2018-08-01
Applicant: SILICON WORKS CO., LTD.
Inventor: Nam Seok SEO , Young Kwang KIM , Young Bok KIM , Hyun Mo YANG , Hae Won LEE , Ju Ho LEE
IPC: G09G3/20
CPC classification number: G09G3/2003 , G09G3/3275 , G09G3/3688 , G09G2310/0248 , G09G2310/0291 , G09G2310/08 , G09G2320/103 , G09G2330/021
Abstract: The present invention discloses a low power driving system and timing controller for a display apparatus. The low power driving system may include: a timing controller configured to divide a display pattern into a static pattern and a dynamic pattern based on a difference between previous line data and current line data, and transmit a packet into which one of first option information corresponding to the static pattern and second option information corresponding to the dynamic pattern is applied; and a source driver configured to receive the packet, and perform a low power mode corresponding to the static pattern according to the first option information or perform adaptive charge sharing corresponding to the dynamic pattern according to the second option information.
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公开(公告)号:US20180144723A1
公开(公告)日:2018-05-24
申请号:US15811921
申请日:2017-11-14
Applicant: SILICON WORKS CO., LTD.
Inventor: Hun Yong LIM , Yong Min KIM , Ju Ho LEE
IPC: G09G5/18
CPC classification number: G09G5/18 , G09G3/20 , G09G3/2092 , G09G2310/0245 , G09G2310/0275 , G09G2310/061 , G09G2310/062 , G09G2310/063 , G09G2310/08
Abstract: Disclosed are a data driving device and a display device including the same. The display device may include: a timing controller configured to include lock fail data in an input signal and transmit the input signal in each preset period; and a source driver configured to recover the lock fail data from the input signal, and reset an internal circuit in response to the recovered lock fail data.
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