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公开(公告)号：US3609243A
公开(公告)日：1971-09-28
申请号：US3609243D
申请日：1969-12-01
发明人： PERNA ALDO
摘要： In a time-allocation telephone system with 96 local lines served by a common switching channel via four two-wire branch channels each allotted to a respective group of 24 lines, an integrating network counts the number of phases in a 100-phase clock cycle during which either wire of a particular branch channel is energized. If the number of unit charges stored in the integrating network during a cycle exceeds the maximum number (48) possible during normal operation, a comparator also receiving a fixed reference voltage trips a flip-flop to inhibit the transmission of switching signals to the main channel from the branch channel in the following cycle. At the beginning of each new cycle, the flip-flop is reset with immediately following discharge of the integrating network.
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2.发明授权
公开(公告)号：US3641275A
公开(公告)日：1972-02-08
申请号：US3641275D
申请日：1969-12-15
发明人： PERNA ALDO , VARDA GIORGIO DE
摘要： A telephone exchange serving a plurality of subscriber groups on a time-sharing basis has an address memory (N) for the code numbers of called (or calling) subscribers and a monitoring memory (P) operating in step therewith to register operational code words in corresponding time slots, there being 100 such time slots of 1 Mu sec. duration in each memory for the establishment of several service phases (000, 001, 002, 003) and a multiplicity of communication phases (004-099) allowing for up to 96 simultaneous conversations over a communication path including a voice lead (Va) and a signal lead (Vs) from which respective branches (Vah, Vsh) extend to each of the several subscriber groups. During a service phase (001) of a cycle in which no caller requests the transmission of ringing current to any called subscriber associated with the exchange, a ringing circuit (Vc) common to all subscriber groups is energized from an audiofrequency generator (GH) for the testing of the voice and signaling circuits of an idle subscriber identified by a code entered in the corresponding time slot of the address memory, the tests proceeding under the control of code words in the same time slot of the monitoring memory which is stepped upon the successful completion of any test. If the subscriber line is found intact, the counter represented by the service phase (001) of the address memory is stepped to register the next higher (or next lower) code number for the testing of another idle subscriber; if a defect is ascertained, an alarm signal is generated which in certain cases inhibits the establishment of any connection between the communication path and the group containing the affected subscriber.
摘要翻译： 以分时为单位服务于多个用户组的电话交换机具有用于被叫（或呼叫）用户的代码号的地址存储器（N）和与其一起操作的监视存储器（P），用于将操作码字注册到 相应的时隙，有100个这样的1个时隙的时隙。 用于建立多个服务阶段（000,001,002,003）和多个通信阶段（004-099）的每个存储器中的持续时间，允许通过包括语音引线（Va）和 一个信号引线（Vs），各个分支（Vah，Vsh）从该信号引线延伸到多个用户组中的每一个。 在没有呼叫者请求向与交换机相关联的任何被叫用户发送振铃电流的周期的服务阶段（001）期间，所有用户组共同的振铃电路（Vc）从音频发生器（GH）激励，用于 通过在地址存储器的相应时隙中输入的代码识别出的空闲用户的语音和信令电路的测试，测试在监视存储器的相同时隙中的代码字的控制下进行， 成功完成任何测试。 如果用户线被发现完好，则由地址存储器的服务阶段（001）表示的计数器被逐步登记用于测试另一个空闲订户的下一个更高（或更低的）代码; 如果确定了缺陷，则产生报警信号，在某些情况下会抑制通信路径与包含受影响用户的组之间的任何连接的建立。
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3.发明授权Signal discriminator for time-sharing communication system having periodic line sampling 失效具有定期线路采样的时间通信系统的信号辨识器
公开(公告)号：US3622997A
公开(公告)日：1971-11-23
申请号：US3622997D
申请日：1970-04-20
发明人： CASELLA LUIGI , PERNA ALDO , VALBONESI GIUSEPPE
摘要： To distinguish between DC pulses of different length detected by periodic sampling of a given transmission line, a data processor evaluates a combination of criteria including the instantaneously sampled line voltage (A), the continuity or lack of continuity of that voltage for a prolonged period (D6''), and the output of the data processor in a preceding sampling interval. This output is preserved, for subsequent reevaluation, in the form of a digital code stored in a time slot of a circulating memory assigned to the line under test. Some of the output signals of the data processor identify transitory conditions which, in the next evaluation cycle, must be converted into one of two possible definite conditions recognized as significant line-voltage criteria.
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公开(公告)号：US3673340A
公开(公告)日：1972-06-27
申请号：US3673340D
申请日：1970-04-20
发明人： CASELLA LUIGI , PERNA ALDO , VALBONESI GIUSEPPE
CPC分类号： H04M3/36
摘要： A monitoring memory (300) of the circulating type has a first section (MC) with 100 phases for the activities of as many local lines identified by two-digit decimal numbers, a second section (MR) subdivided into several multiphase storage units (RET) for receiving, evaluating and transmitting information relating to a call involving an associated local line, and a third section (MS) carrying supplemental information such as the time of day. With 800 phases circulating at a rate of one memory cycle per 800 Mu s, two consecutive counting phases in the third memory section are stepped once per cycle to produce, consecutively, the 100 line-identification numbers or addresses 00-99. A digital counter (100), operating in synchronism with the first section of the monitoring memory, periodically delivers the addresses of the 100 local lines to a comparator (820) matching them with the progressively changing address information stored in the third memory section for a successive sampling of all the lines at intervals of 100 cycles, or 80 ms; this comparison is facilitated by the concurrent tapping of the two consecutive counting phases of the third memory section (MS) whereby the two address digits are simultaneously made available. If a line is found engaged, this information is fed to a logic network (EC) which thereupon seizes an available storage unit (RET) to register the pertinent data in the phases thereof and to feed them to a tape perforator (PF). Upon the response of the called station, or upon premature termination by the calling party, the storage unit (RET) is released; when the call is completed, the same or another such unit and perforator are seized to record the length of the conversation.
摘要翻译： 循环型的监视存储器（300）具有第一部分（MC），其具有100个相位，用于由两位十进制数字标识的许多本地线路的活动;第二部分（MR），被分为多个多相存储单元（RET ），用于接收，评估和发送与涉及本地线路的呼叫有关的信息，以及携带诸如时间之类的补充信息的第三部分（MS）。 800个相位以每800微秒一个存储周期的速率循环，第三存储器部分中的两个连续的计数阶段每循环一个步进一次，连续产生100个行号识别号码或地址00-99。 与监视存储器的第一部分同步操作的数字计数器（100）周期性地将100条本地线路的地址传送到与第三存储器部分中存储的逐渐变化的地址信息相匹配的比较器（820） 以100个周期或80 ms的间隔连续采样所有的线; 通过对第三存储器部分（MS）的两个连续的计数阶段的并发抽头来促进这种比较，从而两个地址数字同时可用。 如果找到一条线，则该信息被馈送到逻辑网络（EC），随后存取可用存储单元（RET），以便在其相位中登记相关数据并将其馈送到磁带穿孔器（PF）。 根据被叫站的响应，或在主叫方过早终止时，存储单元（RET）被释放; 当呼叫完成时，相同或另一个这样的单位和穿孔者被抓住以记录对话的长度。
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公开(公告)号：US3610842A
公开(公告)日：1971-10-05
申请号：US3610842D
申请日：1969-12-16
发明人： FORMENTI FERDINANDO , PERNA ALDO
CPC分类号： H04Q11/04
摘要： A decoder used to emit a succession of commands in the testing of telephone lines, with several output leads only one of which carries a voltage of unit magnitude in any operating condition of the decoder, is checked for correct performance by a network in which a first conductor Y1 is connected to all the output leads Ha...Hn of the decoder through respective diodes D1a...D1n while a second conductor Y2 is connected to these same leads through other diodes Da...Dn in series with respective resistors Ra...Rn. A first comparator CO1 measures the voltage Vy1 of the first conductor against a reference voltage V0 while a second comparator CO2 measures the voltage Vy2 of the second conductor against voltage Vy1; only comparator CO1 has a true output if the decoder functions correctly with a single output lead energized, whereas in all other instances both decoders have outputs of either zero or unity.
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6.发明授权
公开(公告)号：US3603774A
公开(公告)日：1971-09-07
申请号：US3603774D
申请日：1968-06-10
发明人： VARDA GIORGIO DE , MARTINELLI SAVERIO , PERNA ALDO
CPC分类号： H04Q11/04 , G11C21/00 , G11C21/026
摘要： In a telecommunication system of the time-sharing type wherein several calls are concurrently conducted over a common line circuit by means of interleaved message signals recurring in a predetermined order, command pulses relating to the several calls are sequentially directed to the input of a register with several parallel memory stages each including a delay line whose delay time encompasses a number of pulse cycles equal to the maximum number of calls to be accommodated simultaneously by the line circuit. Digital pulses traveling along each memory stage are continuously fed back from the output to the input thereof for reinscription until modified by a command signal applied to all the memory stages through a logic matrix for carrying out such operations as ''''enter 1,'''' ''''enter 0,'''' ''''inscribe new number,'''' ''''add 1'''' and ''''subtract 1.
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