公开(公告)号：US20160042960A1

公开(公告)日：2016-02-11

申请号：US14540866

申请日：2014-11-13

Applicant: SK hynix Inc.

Inventor： Jin Ha KIM ,  Jun Kwan KIM ,  Kang Sik CHOI ,  Su Jin CHAE ,  Young Ho LEE

IPC: H01L21/285 ,  H01L29/78 ,  H01L29/45 ,  H01L27/24

CPC classification number: H01L29/7827 ,  H01L21/28518 ,  H01L21/28531 ,  H01L21/76843 ,  H01L21/76855 ,  H01L27/2454 ,  H01L29/456

Abstract: A 3D semiconductor integrated circuit device and a method of manufacturing the same are provided. An active pillar is formed on a semiconductor substrate, and an interlayer insulating layer is formed so that the active pillar is buried in the interlayer insulating layer. The interlayer insulating layer is etched to form a hole so that the active pillar and a peripheral region of the active pillar are exposed. An etching process is performed on the peripheral region of the active pillar exposed through the hole by a certain depth, and a space having the depth is provided between the active pillar and the interlayer insulating layer. A silicon material layer is formed to be buried in the space having the depth, and an ohmic contact layer is formed on the silicon material layer and the active pillar.

Abstract translation: 提供了一种3D半导体集成电路器件及其制造方法。 在半导体衬底上形成有源柱，并且形成层间绝缘层，使得有源柱埋在层间绝缘层中。 蚀刻层间绝缘层以形成孔，使得活性柱和活性柱的周边区域露出。 在通过孔暴露一定深度的有源柱的周边区域进行蚀刻处理，并且在有源柱和层间绝缘层之间设置具有深度的空间。 形成硅材料层以埋在具有深度的空间中，并且在硅材料层和有源支柱上形成欧姆接触层。

公开(公告)号：US20170084740A1

公开(公告)日：2017-03-23

申请号：US15370922

申请日：2016-12-06

Applicant: SK hynix Inc.

Inventor： Jin Ha KIM ,  Jun Kwan KIM ,  Kang Sik CHOI ,  Su Jin CHAE ,  Young Ho LEE

IPC: H01L29/78 ,  H01L27/24 ,  H01L29/45

CPC classification number: H01L29/7827 ,  H01L21/28518 ,  H01L21/28531 ,  H01L21/76843 ,  H01L21/76855 ,  H01L27/2454 ,  H01L29/456

Abstract: A 3D semiconductor integrated circuit device and a method of manufacturing the same are provided. An active pillar is formed on a semiconductor substrate, and an interlayer insulating layer is formed so that the active pillar is buried in the interlayer insulating layer. The interlayer insulating layer is etched to form a hole so that the active pillar and a peripheral region of the active pillar are exposed. An etching process is performed on the peripheral region of the active pillar exposed through the hole by a certain depth, and a space having the depth is provided between the active pillar and the interlayer insulating layer. A silicon material layer is formed to be buried in the space having the depth, and an ohmic contact layer is formed on the silicon material layer and the active pillar.