公开(公告)号：US12132105B2

公开(公告)日：2024-10-29

申请号：US17571949

申请日：2022-01-10

申请人： Samsung Electronics Co., Ltd.

发明人： Hojun Choi ,  Ji Seong Kim ,  Min Cheol Oh ,  Ki-Il Kim

IPC分类号： H01L27/092 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/7827 ,  H01L21/823814 ,  H01L21/823885 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/42368 ,  H01L29/66666

摘要： There is provided a semiconductor device capable of improving electrical characteristics and integration density. The semiconductor device includes an active pattern protruding from a substrate, the active pattern including long sidewalls extending in a first direction and opposite to each other in a second direction, a lower epitaxial pattern on the substrate and covering a part of the active pattern, a gate electrode on the lower epitaxial pattern and extending along the long sidewalls of the active pattern, and an upper epitaxial pattern on the active pattern and connected to an upper surface of the active pattern. The active pattern includes short sidewalls connecting with the long sidewalls of the active pattern, and at least one of the short sidewalls of the active pattern has a curved surface.

公开(公告)号：US12132098B2

公开(公告)日：2024-10-29

申请号：US17506770

申请日：2021-10-21

申请人： International Business Machines Corporation

发明人： Shogo Mochizuki ,  Choonghyun Lee ,  Kangguo Cheng ,  Juntao Li

IPC分类号： H01L29/66 ,  H01L21/8234 ,  H01L29/78

CPC分类号： H01L29/66666 ,  H01L21/823487 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/7827

摘要： A method of forming a semiconductor structure includes patterning a hard mask layer over a top surface of a substrate. The method also includes forming a first portion of one or more vertical fins below the patterned hard mask layer. The method further includes forming a top spacer on sidewalls of the hard mask layer and the first portion of the one or more vertical fins. The method further includes forming a second portion of the one or more vertical fins in the substrate below the top spacer and trimming sidewalls of the second portion of the one or more vertical fins. The method further includes forming an interfacial layer on the trimmed sidewalls of the second portion of the one or more vertical fins. The one or more vertical fins provide one or more vertical transport channels for one or more vertical transport field-effect transistors.

公开(公告)号：US12132047B2

公开(公告)日：2024-10-29

申请号：US17647672

申请日：2022-01-11

申请人： CHANGXIN MEMORY TECHNOLOGIES, INC.

发明人： Kui Zhang

IPC分类号： H01L27/088 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/092 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234

CPC分类号： H01L27/088 ,  H01L21/8221 ,  H01L21/823828 ,  H01L21/823871 ,  H01L21/823885 ,  H01L27/0688 ,  H01L27/092 ,  H01L29/41741 ,  H01L29/66666 ,  H01L29/7827 ,  H01L21/823475 ,  H01L21/823487

摘要： The present disclosure provides a semiconductor device and a method for manufacturing a semiconductor device. Every two first wires of a first conductive layer of the semiconductor device have a common end, and every two second wires of a second conductive layer of the semiconductor device have a common end.

公开(公告)号：US20240357834A1

公开(公告)日：2024-10-24

申请号：US18757705

申请日：2024-06-28

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Bo-Feng Young ,  Yu-Ming Lin ,  Han-Jong Chia ,  Sheng-Chen Wang ,  Sai-Hooi Yeong

IPC分类号： H10B53/30 ,  H01L29/66 ,  H01L29/78 ,  H10B53/00 ,  H10B53/20

CPC分类号： H10B53/30 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/7831 ,  H01L29/7841 ,  H10B53/00 ,  H10B53/20

摘要： A gated ferroelectric memory cell includes a dielectric material layer disposed over a substrate, a metallic bottom electrode, a ferroelectric dielectric layer contacting a top surface of the bottom electrode, a pillar semiconductor channel overlying the ferroelectric dielectric layer and capacitively coupled to the metallic bottom electrode through the ferroelectric dielectric layer, a gate dielectric layer including a horizontal gate dielectric portion overlying the ferroelectric dielectric layer and a tubular gate dielectric portion laterally surrounding the pillar semiconductor channel, a gate electrode strip overlying the horizontal gate dielectric portion and laterally surrounding the tubular gate dielectric portion and a metallic top electrode contacting a top surface of the pillar semiconductor channel.

公开(公告)号：US20240339523A1

公开(公告)日：2024-10-10

申请号：US18063987

申请日：2022-12-09

申请人： International Business Machines Corporation

发明人： Tsung-Sheng Kang ,  Tao Li ,  Ruilong Xie ,  Julien Frougier ,  Reinaldo Vega

IPC分类号： H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L29/78

CPC分类号： H01L29/66795 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/7827 ,  H01L29/7851

摘要： One or more devices and/or methods provided herein relate to a method for fabricating a semiconductor device, and more particularly for fabricating at least a portion of a vertical transport field effect transistor. The semiconductor device comprises a field-effect transmitter comprising a substrate, a fin extending outwardly from the substrate, a source/drain region having a first portion disposed between the substrate and the fin and stacked with the fin and the substrate along a common extension direction of the fin, and an excess section of semiconductor material disposed adjacent the first portion of the source/drain region and positioned other than stacked together with the substrate and the fin, wherein the semiconductor material of the excess section is different from a material of the fin and different from a material of the source/drain region.

公开(公告)号：US12114474B2

公开(公告)日：2024-10-08

申请号：US17877628

申请日：2022-07-29

申请人： Micron Technology, Inc.

发明人： Scott J. Derner ,  Charles L. Ingalls

IPC分类号： G11C11/24 ,  G11C11/4091 ,  G11C11/4094 ,  H01L29/78 ,  H10B12/00

CPC分类号： H10B12/00 ,  G11C11/4091 ,  G11C11/4094 ,  H01L29/78 ,  H01L29/7827 ,  H10B12/50

摘要： Some embodiments include an integrated assembly having a primary access transistor. The primary access transistor has a first source/drain region and a second source/drain region. The first and second source/drain regions are coupled to one another when the primary access transistor is in an ON mode, and are not coupled to one another when the primary access transistor is in an OFF mode. A charge-storage device is coupled with the first source/drain region. A digit line is coupled with the second source/drain region through a secondary access device. The secondary access device has an ON mode and an OFF mode. The digit line is coupled with the charge-storage device only when both the primary access transistor and the secondary access device are in their respective ON modes.

公开(公告)号：US12108606B2

公开(公告)日：2024-10-01

申请号：US17892514

申请日：2022-08-22

申请人： SK hynix Inc.

发明人： Jae Hyun Han ,  Jae Gil Lee ,  Hyangkeun Yoo ,  Se Ho Lee

IPC分类号： H10B51/20 ,  H01L29/78 ,  H01L29/786 ,  H01L29/788 ,  H10B51/10

CPC分类号： H10B51/20 ,  H01L29/7827 ,  H01L29/78391 ,  H01L29/78642 ,  H01L29/78696 ,  H01L29/7889 ,  H10B51/10

摘要： A nonvolatile memory device includes a substrate having an upper surface, and a gate structure disposed over the substrate. The gate structure includes at least one gate electrode layer pattern and at least one gate insulation layer pattern, which are alternately stacked along a first direction perpendicular to the upper surface. The gate structure extends in a second direction perpendicular to the first direction. The nonvolatile memory device includes a ferroelectric layer disposed on at least a portion of one sidewall surface of the gate structure. The one sidewall surface of the gate structure forms a plane substantially parallel to the first and second directions. The nonvolatile memory device includes a channel layer disposed on the ferroelectric layer, and a source electrode structure and a drain electrode structure disposed to contact the channel layer and spaced apart from each other in the second direction.

公开(公告)号：US20240312913A1

公开(公告)日：2024-09-19

申请号：US18184085

申请日：2023-03-15

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shang-Wen Chang ,  Cheng-Chi Chuang ,  Ching-Wei Tsai ,  Yi-Hsun Chiu ,  Yu-Xuan Huang

IPC分类号： H01L23/528 ,  H01L21/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L23/5286 ,  H01L21/7806 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/823885 ,  H01L27/092 ,  H01L29/41741 ,  H01L29/66666 ,  H01L29/7827

摘要： A method includes forming a vertical transistor, and the method includes forming a vertical semiconductor bar over a substrate, forming a gate dielectric and a gate electrode encircling the vertical semiconductor bar, forming a first source/drain region over a top surface of the vertical semiconductor bar, removing the substrate to reveal a bottom surface of the vertical semiconductor bar; and forming a second source/drain region contacting the bottom surface of the vertical semiconductor bar. The method further includes forming a backside power line, with the backside power line being on a bottom side of the vertical semiconductor bar. The backside power line is connected to the second source/drain region.

公开(公告)号：US20240304722A1

公开(公告)日：2024-09-12

申请号：US18424704

申请日：2024-01-26

申请人： Micron Technology, Inc.

发明人： Darwin A. Clampitt ,  Roger W. Lindsay ,  Martin J. Barclay

IPC分类号： H01L29/78 ,  H10B41/27 ,  H10B43/27

CPC分类号： H01L29/7827 ,  H10B41/27 ,  H10B43/27

摘要： A microelectronic device comprises a stack structure comprising a vertically alternating sequence of conductive structures and insulative structures arranged in tiers, a staircase structure comprising steps comprising horizontal edges of the tiers, each of the steps comprising multiple tiers, and conductive contact structures vertically extending from a vertically upper surface of the stack structure to the conductive structures of the steps, the conductive structures defining each of the steps individually in contact with a conductive contact structure. Related memory devices and electronic systems are also described.

公开(公告)号：US12089412B2

公开(公告)日：2024-09-10

申请号：US16831623

申请日：2020-03-26

申请人： INTEL NDTM US LLC

发明人： Dong Ji ,  Guangyu Huang ,  Deepak Thimmegowda

IPC分类号： H10B43/40 ,  H01L21/02 ,  H01L29/04 ,  H01L29/06 ,  H01L29/16 ,  H01L29/22 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27

CPC分类号： H10B43/40 ,  H01L21/02532 ,  H01L21/02554 ,  H01L21/02595 ,  H01L29/04 ,  H01L29/0634 ,  H01L29/16 ,  H01L29/22 ,  H01L29/4916 ,  H01L29/66666 ,  H01L29/66969 ,  H01L29/7827 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27

摘要： A driver circuit for a three-dimensional (3D) memory device has a super junction structure as a field management structure. The super junction structure could be referred to as an extended junction structure, which distributes the electrical field of the junction between the vertical channel and the gate conductor for a string driver. The vertical channel includes a channel conductor to connect vertically between a source conductor and a drain conductor. The extended junction structure extends in parallel with the vertical channel conductor, extending vertically toward the drain conductor, having a height greater than a height of the gate conductor.