公开(公告)号：US20140015601A1

公开(公告)日：2014-01-16

申请号：US13724143

申请日：2012-12-21

Applicant: SK HYNIX INC.

Inventor： Kyoung Youn LEE

IPC: H02M3/158

CPC classification number: H02M3/158 ,  G05F1/00 ,  G11C5/147

Abstract: A power supply circuit to supply an internal voltage to an output node includes: a pull-up driver, in response to a result obtained by comparing the internal voltage to a first reference voltage, configured to generate the internal voltage from a power supply voltage, a pull-down driver, in response to a result obtained by comparing the internal voltage to a second reference voltage, configured to discharge the internal voltage, a pull-up drive blocking unit configured to block the pull-up driver from being driven, in response to the result obtained by comparing the internal voltage to the second reference voltage, and a pull-down drive blocking unit configured to block the pull-down driver from being driven, in response to the result obtained by comparing the internal voltage to the first reference voltage.

Abstract translation: 向输出节点提供内部电压的电源电路包括：上拉驱动器，响应于通过将内部电压与第一参考电压进行比较而获得的结果，被配置为从电源电压产生内部电压， 下拉驱动器，响应于通过将内部电压与第二参考电压进行比较而获得的结果，被配置为对内部电压进行放电，被配置为阻止上拉驱动器被驱动的上拉驱动阻断单元， 响应于通过将内部电压与第二参考电压进行比较获得的结果，以及被配置为阻止下拉驱动器被驱动的下拉驱动阻断单元，响应于通过将内部电压与第一 参考电压。

公开(公告)号：US20200013450A1

公开(公告)日：2020-01-09

申请号：US16212407

申请日：2018-12-06

Applicant: SK hynix Inc.

Inventor： Seung Min YANG ,  Kyoung Youn LEE ,  Byeong Cheol LEE ,  Don Hyun CHOI

IPC: G11C11/4076 ,  G11C11/406 ,  G11C11/408

Abstract: A semiconductor device includes a delay time adjustment circuit and an address input circuit. The delay time adjustment circuit adjusts a point in time when charges are supplied to internal nodes according to a voltage level of a back-bias voltage in response to a test mode signal. The delay time adjustment circuit also delays an active signal by a first delay time varying according to amounts of charge of the internal nodes to generate a bank selection signal. The address input circuit is driven by the back-bias voltage. The address input circuit receives an address in response to the bank selection signal to generate an internal address. The address input circuit delays the address by a second delay time varying according to a voltage level of the back-bias voltage.

公开(公告)号：US20140049245A1

公开(公告)日：2014-02-20

申请号：US13724355

申请日：2012-12-21

Applicant: SK HYNIX INC.

Inventor： Young Ran KIM ,  Jae Boum PARK ,  Kyoung Youn LEE

IPC: G05F1/46

CPC classification number: G05F1/468

Abstract: A reference voltage generation circuit includes: a reference voltage generation unit configured to generate a plurality of reference voltages having mutually different temperature characteristics, a switching unit configured to select and output one of the plurality of reference voltages in response to a control signal, a temperature detection unit configured to detect temperature change and to output a temperature detection signal, and a control unit configured to generate the control signal in response to the temperature detection to signal.

Abstract translation: 参考电压产生电路包括：参考电压生成单元，被配置为产生具有相互不同的温度特性的多个参考电压;开关单元，被配置为响应于控制信号选择并输出多个参考电压中的一个，温度 检测单元，被配置为检测温度变化并输出温度检测信号;以及控制单元，被配置为响应于所述温度检测而产生所述控制信号以进行信号。