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    SEMICONDUCTOR DEVICES
    1.
    发明申请
    SEMICONDUCTOR DEVICES 审中-公开

    公开(公告)号：US20200013450A1

    公开(公告)日：2020-01-09

    申请号：US16212407

    申请日：2018-12-06

    Applicant: SK hynix Inc.

    Inventor： Seung Min YANG ,  Kyoung Youn LEE ,  Byeong Cheol LEE ,  Don Hyun CHOI

    IPC: G11C11/4076 ,  G11C11/406 ,  G11C11/408

    Abstract: A semiconductor device includes a delay time adjustment circuit and an address input circuit. The delay time adjustment circuit adjusts a point in time when charges are supplied to internal nodes according to a voltage level of a back-bias voltage in response to a test mode signal. The delay time adjustment circuit also delays an active signal by a first delay time varying according to amounts of charge of the internal nodes to generate a bank selection signal. The address input circuit is driven by the back-bias voltage. The address input circuit receives an address in response to the bank selection signal to generate an internal address. The address input circuit delays the address by a second delay time varying according to a voltage level of the back-bias voltage.

    CONTROL CIRCUIT FOR BIT-LINE SENSE AMPLIFIER AND SEMICONDUCTOR MEMORY APPARATUS HAVING THE SAME, AND OPERATING METHOD THEREOF
    2.
    发明申请
    CONTROL CIRCUIT FOR BIT-LINE SENSE AMPLIFIER AND SEMICONDUCTOR MEMORY APPARATUS HAVING THE SAME, AND OPERATING METHOD THEREOF 有权
    用于位线检测放大器的控制电路和具有该放大器的半导体存储器件及其操作方法

    公开(公告)号：US20150155018A1

    公开(公告)日：2015-06-04

    申请号：US14173953

    申请日：2014-02-06

    Applicant: SK hynix Inc.

    Inventor： Byeong Cheol LEE

    IPC: G11C7/22 ,  G11C7/08 ,  G11C7/12

    CPC classification number: G11C7/222 ,  G11C7/08 ,  G11C8/12 ,  G11C11/4091

    Abstract: A control circuit for a bit-line sense amplifier may include: a bank active signal generator configured to generate an internal active signal and a bank active signal; and a sense amplifier enable signal generator configured to determine a skew in response to the internal active signal, and set an output time of a sense amplifier enable signal by delaying the bank active signal according to the determined skew.

    Abstract translation: 用于位线读出放大器的控制电路可以包括：存储体有源信号发生器，其被配置为产生内部有源信号和存储体有效信号; 以及读出放大器使能信号发生器，被配置为响应于所述内部有源信号确定偏斜，并且通过根据所确定的偏差来延迟所述存储体有效信号来设置读出放大器使能信号的输出时间。

    SEMICONDUCTOR DEVICE PROVIDING A TEST MODE RELATED TO DETECTING A DEFECT IN A METAL LINE
    3.
    发明申请
    SEMICONDUCTOR DEVICE PROVIDING A TEST MODE RELATED TO DETECTING A DEFECT IN A METAL LINE 有权

    公开(公告)号：US20240404614A1

    公开(公告)日：2024-12-05

    申请号：US18480027

    申请日：2023-10-03

    Applicant: SK hynix Inc.

    Inventor： Byeong Cheol LEE

    IPC: G11C29/02 ,  G11C8/08

    Abstract: A semiconductor device including a main word line driver connected to a metal line and configured to transmit a main word line signal to the metal line in order to access at least one of memory cells that are included in a core circuit, the core circuit connected to the metal line and configured to transmit, as a delay main word line signal, the main word line signal that is received through the metal line. The semiconductor device including a test mode control circuit connected to the metal line. The test mode control circuit configured to receive the delay main word line signal through the metal line. The test mode control circuit configured to perform a test mode in which the test mode control circuit drives the metal line in response to the delay main word line signal.

    POWER CONTROL CIRCUIT, SEMICONDUCTOR APPARATUS INCLUDING THE SAME AND POWER CONTROL METHOD OF SEMICONDUCTOR APPARATUS
    4.
    发明申请
    POWER CONTROL CIRCUIT, SEMICONDUCTOR APPARATUS INCLUDING THE SAME AND POWER CONTROL METHOD OF SEMICONDUCTOR APPARATUS 有权

    公开(公告)号：US20220101907A1

    公开(公告)日：2022-03-31

    申请号：US17550635

    申请日：2021-12-14

    Applicant: SK hynix Inc.

    Inventor： Woongrae KIM ,  Byeong Cheol LEE ,  Se Won LEE

    IPC: G11C11/4074 ,  G11C11/406 ,  G11C8/10

    Abstract: A power control circuit includes a power control signal generation circuit configured to generate a voltage control signal according to a deep sleep command for operating a semiconductor apparatus in a deep sleep mode; a voltage divider circuit having a division ratio that is changed according to the voltage control signal, and configured to generate a divided voltage by dividing an internal voltage at the changed division ratio; a comparator configured to generate a detection signal by comparing a reference voltage to the divided voltage; an oscillator configured to generate an oscillation signal according to the detection signal; and a pump configured to generate the internal voltage according to the oscillation signal.

    POWER CONTROL CIRCUIT, SEMICONDUCTOR APPARATUS INCLUDING THE SAME AND POWER CONTROL METHOD OF SEMICONDUCTOR APPARATUS
    5.
    发明申请
    POWER CONTROL CIRCUIT, SEMICONDUCTOR APPARATUS INCLUDING THE SAME AND POWER CONTROL METHOD OF SEMICONDUCTOR APPARATUS 审中-公开

    公开(公告)号：US20200211616A1

    公开(公告)日：2020-07-02

    申请号：US16661342

    申请日：2019-10-23

    Applicant: SK hynix Inc.

    Inventor： Woongrae KIM ,  Byeong Cheol LEE ,  Se Won LEE

    IPC: G11C11/4074 ,  G11C8/10 ,  G11C11/406

    Abstract: A power control circuit includes a power control signal generation circuit configured to generate a voltage control signal according to a deep sleep command for operating a semiconductor apparatus in a deep sleep mode; a voltage divider circuit having a division ratio that is changed according to the voltage control signal, and configured to generate a divided voltage by dividing an internal voltage at the changed division ratio; a comparator configured to generate a detection signal by comparing a reference voltage to the divided voltage; an oscillator configured to generate an oscillation signal according to the detection signal; and a pump configured to generate the internal voltage according to the oscillation signal.

    SEMICONDUCTOR DEVICE FOR DETECTING DEFECT IN WORD LINE DRIVER
    9.
    发明公开
    SEMICONDUCTOR DEVICE FOR DETECTING DEFECT IN WORD LINE DRIVER 审中-公开

    公开(公告)号：US20240290415A1

    公开(公告)日：2024-08-29

    申请号：US18341607

    申请日：2023-06-26

    Applicant: SK hynix Inc.

    Inventor： Byeong Cheol LEE

    IPC: G11C29/46 ,  G11C29/36

    CPC classification number: G11C29/46 ,  G11C29/36 ,  G11C2029/1202

    Abstract: A semiconductor device includes a test control circuit configured to enter a test mode and configured to generate a test word line precharge signal, based on a test mode entry signal, an active pulse, a precharge pulse, a reset signal, and a test code; a mat including a plurality of word line drivers; and a word line control circuit configured to generate a word line driving signal, a plurality of voltage driving signals, and a plurality of voltage discharge signals for controlling operations of the plurality of word line drivers, based on the test word line precharge signal, a mat enable signal, and a plurality of internal addresses. The word line driving signal is a signal that is enabled after a start of an active operation and that is disabled after a set period from timing for a precharge operation.

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