公开(公告)号：US20220237041A1

公开(公告)日：2022-07-28

申请号：US17472082

申请日：2021-09-10

Applicant: SK hynix Inc. ,  Korea University Research and Business Foundation

Inventor： Wonjun LEE ,  Changhyun KIM ,  Seonwook KIM

IPC: G06F9/50 ,  G06F9/38 ,  G06F9/54

Abstract: A parallel processing system includes a host and a memory device. The host includes a central processing unit configured to process processing in-memory (PIM) requests generated in a plurality of threads for in-memory processing and a memory controller configured to generate a PIM command corresponding to the PIM request. The memory device including a plurality of computing cores each including a bank and a computing circuit. The memory device is configured to perform in-memory processing in one of the plurality of computing cores according to the PIM command. The host allocates the plurality of computing cores to the plurality of threads, and PIM commands of each thread are processed using the computing core allocated to that thread.

公开(公告)号：US20220222251A1

公开(公告)日：2022-07-14

申请号：US17469857

申请日：2021-09-08

Applicant: SK hynix Inc. ,  Korea University Research and Business Foundation

Inventor： Seok Young KIM ,  Changhyun KIM ,  Wonjun LEE ,  Seonwook KIM

IPC: G06F16/2455 ,  G06F7/57

Abstract: A semiconductor device includes a look-up table storing a plurality of input values defining a plurality of sections, wherein a range of function values corresponding to the plurality of input values is equally divided into the plurality of sections; and an operation circuit configured to receive a given input value, determine a target section where the given input value is included by searching the look-up table, and determine a function value corresponding to the given input value based on the target section.

公开(公告)号：US20220157371A1

公开(公告)日：2022-05-19

申请号：US17401201

申请日：2021-08-12

Applicant: SK hynix Inc. ,  Korea University Research and Business Foundation

Inventor： Seonwook KIM ,  Wonjun LEE ,  Changhyun KIM

IPC: G11C11/4096 ,  G06F7/544 ,  G06F7/50 ,  G06F7/523

Abstract: A semiconductor device includes a memory cell array, an address input circuit, a command input circuit, a data Input/Output (JO) circuit, a processing control circuit, a processing circuit, and a switch circuit. The processing control circuit includes a register array storing an address of an operand and determines whether an address provided from the address input circuit corresponds to the address stored in the register array. The processing circuit is configured to provide a processing result by performing an operation on data provided from the memory cell array. The switch circuit is configured to control a data path among the processing circuit, the data JO circuit, and the memory cell array and controls the data path to connect the memory cell array to the processing circuit when the address provided from the address input circuit corresponds to the address stored in the register array.

公开(公告)号：US20200293453A1

公开(公告)日：2020-09-17

申请号：US16890706

申请日：2020-06-02

Applicant: SK hynix Inc. ,  Korea University Industry Cooperation Foundation

Inventor： Seonwook KIM ,  Wonjun LEE ,  Yoonah PAIK ,  Jaeyung JUN

IPC: G06F12/0886 ,  G06F12/0891

Abstract: A computing system using a bit counter may include a host device; a cache configured to temporarily store data of the host device, and including a plurality of sets; a cache controller configured to receive a multi-bit cache address from the host device, perform computation on the cache address using a plurality of bit counters, and determine a hash function of the cache; a semiconductor device; and a memory controller configured to receive the cache address from the cache controller, and map the cache address to a semiconductor device address.