公开(公告)号：US11757683B2

公开(公告)日：2023-09-12

申请号：US17698918

申请日：2022-03-18

申请人： SK hynix Inc. ,  Seoul National University R&DB Foundation

发明人： Daeho Yun ,  Deog-Kyoon Jeong

IPC分类号： H04L25/03 ,  H04L27/01

CPC分类号： H04L25/03885 ,  H04L25/03057 ,  H04L27/01

摘要： A receiver includes a plurality of linear equalizers receiving an input signal; and a plurality of samplers configured to sample a plurality of equalization signals output from the plurality of linear equalizers according to a clock signal. Each of the plurality of linear equalizers compares the input signal with a reference voltage among a plurality of reference voltages to determine a level of the input signal.