公开(公告)号：US20210374131A1

公开(公告)日：2021-12-02

申请号：US17118085

申请日：2020-12-10

申请人： SK hynix Inc. ,  Seoul National University R&DB Foundation

发明人： Jun HEO ,  Jaeyeon WON ,  Yejin LEE ,  Jaeyoung JANG ,  Tae Jun HAM ,  Jae Wook LEE

IPC分类号： G06F16/2455 ,  G06F16/2457 ,  G06F16/248 ,  G06F16/28 ,  G06F16/22

摘要： A hardware accelerator includes a block processing circuit configured to read a block from a list stored in an inverted index structure; and a search core configured to extract a document number out of a read block read by the block processing circuit and to calculate a score corresponding to the document number.

公开(公告)号：US20220253682A1

公开(公告)日：2022-08-11

申请号：US17375197

申请日：2021-07-14

申请人： Samsung Electronics Co., Ltd. ,  Seoul National University R&DB Foundation

发明人： Seung Wook LEE ,  Jaeyeon WON ,  Jae Wook LEE ,  Tae Jun HAM

IPC分类号： G06N3/063 ,  G06F7/544 ,  G06F7/523 ,  G06F7/50 ,  G06F7/76 ,  G06F5/01

摘要： A processor, a method of operating the processor, and an electronic device including the processor are disclosed. The method includes arranging, in respective input registers, weights and activations having a smaller number of bits than a minimum operation unit of an operator included in the processor, performing a multiplication between values stored in the input registers, storing a result of the multiplication in an output register, and outputting, from the output register, a value in a preset bit range as a result of a dot product between a first vector including the weights and a second vector including the activations.