公开(公告)号：US20210258016A1

公开(公告)日：2021-08-19

申请号：US17173053

申请日：2021-02-10

Applicant: SOCIONEXT INC.

Inventor： Armin JALILI SEBARDAN ,  Alistair John GRATREX ,  Mojtaba BAGHERI

IPC: H03M1/12

Abstract: A sampling switch circuit, comprising: an input node, connected to receive an input voltage signal to be sampled; a sampling transistor comprising a gate terminal, a source terminal and a drain terminal, the source terminal connected to the input node; a potential divider circuit connected to the input node and a track-control node to provide a track-control voltage signal dependent on the input voltage signal at the track-control node; a hold-control node connected to receive a hold-control voltage signal; an output node connected to the drain terminal of the sampling transistor; and switching circuitry configured to connect the gate terminal of the sampling transistor to the track-control node or to the hold-control node in dependence upon a clock signal.

公开(公告)号：US20220239265A1

公开(公告)日：2022-07-28

申请号：US17716725

申请日：2022-04-08

Applicant: SOCIONEXT INC.

Inventor： Armin JALILI SEBARDAN ,  Alistair John GRATREX

IPC: H03F3/45 ,  H03F1/32

Abstract: Differential amplifier circuitry including: first and second main transistors of a given conductivity type; and first and second auxiliary transistors of an opposite conductivity type, where the first and second main transistors are connected along first and second main current paths passing between first and second main voltage reference nodes and first and second output nodes, respectively, with their source terminals connected to the first and second output nodes, respectively, and with their gate terminals controlled by component input signals of a differential input signal; and the first and second auxiliary transistors are connected along first and second auxiliary current paths passing between first and second auxiliary voltage reference nodes and the first and second output nodes, respectively, with their drain terminals connected to the first and second output nodes, respectively, and with their gate terminals controlled by the component input signals of the differential input signal.