公开(公告)号：US10446492B2

公开(公告)日：2019-10-15

申请号：US15982766

申请日：2018-05-17

Applicant: SOCIONEXT INC.

Inventor： Tooru Matsui ,  Masahiro Yoshimura

IPC: H01L23/52 ,  H01L23/528 ,  H01L23/60 ,  H02H9/04 ,  H01L27/02

Abstract: Disclosed herein is a configuration for ensuring sufficient power supply ability and ESD protection capability for I/O cells in a semiconductor integrated circuit device, without increasing its circuit area. In two I/O cell rows, a pair of I/O cells for supplying a power supply potential or ground potential are connected together via a common power supply interconnect. The I/O cells are arranged so as to overlap with each other in a first direction in which the I/O cells are arranged. The common power supply interconnect extends in a second direction perpendicular to the first direction, and is connected to first pads that are located closest in the first direction to the common power supply interconnect.

公开(公告)号：US10438939B2

公开(公告)日：2019-10-08

申请号：US16218149

申请日：2018-12-12

Applicant: SOCIONEXT INC.

Inventor： Tooru Matsui

IPC: H01L23/52 ,  H01L27/02 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/528 ,  H01L23/00 ,  H02H9/04

Abstract: Disclosed herein is a configuration for ensuring ESD protection capability for a core power supply of a semiconductor integrated circuit device, without causing an increase in the circuit area. A first pad row in a core region includes a first pad for core power supply. The first pad is connected to a core power supply interconnect, and supplied with a power supply potential or a ground potential. A second pad row provided outwardly from the first pad row includes a second pad for core power supply. The second pad is supplied with the same power supply or ground potential as the first pad for core power supply, and connected to an I/O cell for core power supply.

公开(公告)号：US10186504B2

公开(公告)日：2019-01-22

申请号：US15493321

申请日：2017-04-21

Applicant: SOCIONEXT INC.

Inventor： Tooru Matsui

IPC: H01L23/52 ,  H01L27/02 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/528 ,  H01L23/00 ,  H02H9/04

Abstract: Disclosed herein is a configuration for ensuring ESD protection capability for a core power supply of a semiconductor integrated circuit device, without causing an increase in the circuit area. A first pad row in a core region includes a first pad for core power supply. The first pad is connected to a core power supply interconnect, and supplied with a power supply potential or a ground potential. A second pad row provided outwardly from the first pad row includes a second pad for core power supply. The second pad is supplied with the same power supply or ground potential as the first pad for core power supply, and connected to an I/O cell for core power supply.

公开(公告)号：US10002832B2

公开(公告)日：2018-06-19

申请号：US15493338

申请日：2017-04-21

Applicant: SOCIONEXT INC.

Inventor： Tooru Matsui ,  Masahiro Yoshimura

IPC: H01L21/82 ,  H01L23/528 ,  H02H9/04 ,  H01L23/60

CPC classification number: H01L23/5286 ,  H01L23/60 ,  H01L27/0207 ,  H02H9/046

Abstract: Disclosed herein is a configuration for ensuring sufficient power supply ability and ESD protection capability for I/O cells in a semiconductor integrated circuit device, without increasing its circuit area. In two I/O cell rows, a pair of I/O cells for supplying a power supply potential or ground potential are connected together via a common power supply interconnect. The I/O cells are arranged so as to overlap with each other in a first direction in which the I/O cells are arranged. The common power supply interconnect extends in a second direction perpendicular to the first direction, and is connected to first pads that are located closest in the first direction to the common power supply interconnect.