公开(公告)号：US11687699B2

公开(公告)日：2023-06-27

申请号：US17771967

申请日：2021-12-11

Applicant: SOUTHEAST UNIVERSITY

Inventor： Fujin Deng ,  Yun Zhou ,  Hanlu Zhang ,  Chengkai Liu ,  Jianzhong Zhang

IPC: G06F30/00 ,  G06F30/398 ,  H02J3/38

CPC classification number: G06F30/398 ,  H02J3/381 ,  H02J2203/20

Abstract: The present invention discloses a method for modeling sequence impedance of a modular multilevel converter (MMC) under phase locked loop (PLL) coupling. The method includes the following steps: S1, establishing a circuit topology model; S2, establishing a PLL output characteristic model; S3, establishing a PI controller output control small signal model under a dq axis; S4, deducing a modulation small signal; and S5, calculating MMC port impedance. According to the method, a precise MMC port impedance model is established by analyzing a double mirror frequency coupling effect in the output of a modulation signal in a control link caused by a phase angle disturbance and comprehensively considering the combination of the multi-harmonic coupling effect of an MMC. On one hand, the proposed modeling method aims at a common MMC adopting current closed-loop control, in which a half-bridge sub-module is adopted, a circuit topological structure and a control structure are both more common, and a mathematical model is easy to establish. On the other hand, the physical significance of an impedance analysis method is clear, the modeling process is modular and is easy to understand and implement, and the inverter port impedance can be measured on site, so that the correctness of theoretical modeling can be conveniently verified.