公开(公告)号：US12061854B1

公开(公告)日：2024-08-13

申请号：US18571727

申请日：2023-01-03

Applicant: SOUTHEAST UNIVERSITY

Inventor： Peng Cao ,  Qianqian Song ,  Kai Wang

IPC: G06F30/30 ,  G06F30/337 ,  G06F119/06

CPC classification number: G06F30/337 ,  G06F2119/06

Abstract: An optimization method for a digital integrated circuit is provided. Under the precondition of satisfying certain timing constraints, circuit-level, path-level and gate cell-level features of a circuit are extracted to construct a leakage power optimization model, and optimization data from commercial circuit optimization tools is used to train the model to predict voltage threshold types of gate cells after circuit optimization, such that the circuit can be optimized by adjusting voltage thresholds of gate cells in a post-routing gate-level netlist, thus realizing the optimization objective of reducing leakage power.