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11 条记录 (耗时 0.015 秒)

    Optimization method for digital integrated circuit
    1.
    发明授权
    Optimization method for digital integrated circuit 有权

    公开(公告)号：US12061854B1

    公开(公告)日：2024-08-13

    申请号：US18571727

    申请日：2023-01-03

    申请人： SOUTHEAST UNIVERSITY

    发明人： Peng Cao ,  Qianqian Song ,  Kai Wang

    IPC分类号： G06F30/30 ,  G06F30/337 ,  G06F119/06

    CPC分类号： G06F30/337 ,  G06F2119/06

    摘要： An optimization method for a digital integrated circuit is provided. Under the precondition of satisfying certain timing constraints, circuit-level, path-level and gate cell-level features of a circuit are extracted to construct a leakage power optimization model, and optimization data from commercial circuit optimization tools is used to train the model to predict voltage threshold types of gate cells after circuit optimization, such that the circuit can be optimized by adjusting voltage thresholds of gate cells in a post-routing gate-level netlist, thus realizing the optimization objective of reducing leakage power.

    Flexible modeling method for timing constraint of register
    2.
    发明授权
    Flexible modeling method for timing constraint of register 有权

    公开(公告)号：US11790142B2

    公开(公告)日：2023-10-17

    申请号：US18014002

    申请日：2022-03-09

    申请人： SOUTHEAST UNIVERSITY

    发明人： Peng Cao ,  Haiyang Jiang ,  Jiahao Wang

    IPC分类号： G06F30/3312 ,  G06F30/3315 ,  G06F119/12

    CPC分类号： G06F30/3312 ,  G06F30/3315 ,  G06F2119/12

    摘要： Disclosed in the present invention is a flexible modeling method for a timing constraint of a register. Simulation ranges of input terminal transition time, clock terminal transition time, and output load capacitance of a register are determined first, simulation is performed under each combination of input terminal transition time, clock terminal transition time, and output load capacitance to obtain a timing constraint range, then setup slack and hold slack are extracted in this constraint range with a particular interval, and then simulation is performed to obtain a clock terminal-to-output terminal delay. Finally, a mutually independent timing model of the register is established by using an artificial neural network, where the clock terminal-to-output terminal delay is modeled as a function of the input terminal transition time, the clock terminal transition time, the output load capacitance, the setup slack, the hold slack, and an output terminal state. A flexible timing constraint model in the present invention has advantages of low simulation overheads and high prediction precision, and is of great significance for static timing analysis timing signoff of a digital integrated circuit.

    Method for predicting delay at multiple corners for digital integrated circuit
    3.
    发明授权
    Method for predicting delay at multiple corners for digital integrated circuit 有权

    公开(公告)号：US11755807B2

    公开(公告)日：2023-09-12

    申请号：US18010131

    申请日：2022-03-09

    申请人： SOUTHEAST UNIVERSITY

    发明人： Peng Cao ,  Kai Wang ,  Tai Yang ,  Wei Bao

    IPC分类号： G06F30/367 ,  G06N3/0442 ,  G06N3/0464 ,  G06N3/045 ,  G06F119/06 ,  G06F119/12

    CPC分类号： G06F30/367 ,  G06N3/045 ,  G06N3/0442 ,  G06N3/0464 ,  G06F2119/06 ,  G06F2119/12

    摘要： Disclosed in the present invention is a method for predicting a delay at multiple corners for a digital integrated circuit, which is applicable to the problem of timing signoff at multiple corners. In the aspect of feature engineering, a path delay relationship at adjacent corners is extracted by using a dilated convolutional neural network (Dilated CNN), and learning is performed by using a bi-directional long short-term memory model (Bi-directional Long Short-Term Memory, BLSTM) to obtain topology information of a path. Finally, prediction results of a path delay at a plurality of corners are obtained by using an output of a multi-gate mixture-of-experts network model (Multi-gate Mixture-of-Experts, MMoE). Compared with a conventional machine learning method, the present invention can achieve prediction with higher precision through more effective feature engineering processing in a case of low simulation overheads, and is of great significance for timing signoff at multiple corners of a digital integrated circuit.

    Method for optimizing circuit timing based on flexible register timing library
    5.
    发明授权
    Method for optimizing circuit timing based on flexible register timing library 有权

    公开(公告)号：US11829693B2

    公开(公告)日：2023-11-28

    申请号：US18011443

    申请日：2022-03-09

    申请人： SOUTHEAST UNIVERSITY

    发明人： Peng Cao ,  Jiahao Wang ,  Haiyang Jiang

    IPC分类号： G06F30/3315 ,  G06F30/337 ,  G06F119/12

    CPC分类号： G06F30/3315 ,  G06F30/337 ,  G06F2119/12

    摘要： Disclosed in the present invention is a method for optimizing circuit timing based on a flexible register timing library. First, registers are simulated respectively in a case of a plurality of groups of an input signal conversion time, a clock signal conversion time, and a register load capacitance, corresponding actual propagation delays at this time are obtained by changing setup slack and hold slack of the registers, and actual propagation delays of the registers under specific input signal conversion time, clock signal conversion time, register load capacitances, setup slack, and hold slack are obtained through linear interpolation, to establish a flexible register timing library; and then static timing analysis is performed on all register paths in a circuit by using the library, a minimum clock cycle under a condition of satisfying that a setup time margin and a hold time margin are both greater than zero is found by changing the setup slack and hold slack of the registers, thereby improving the performance of the circuit without changing the design of the circuit and without increasing the area overheads of the circuit.

    Post-routing path delay prediction method for digital integrated circuit
    8.
    发明授权
    Post-routing path delay prediction method for digital integrated circuit 有权

    公开(公告)号：US12056428B1

    公开(公告)日：2024-08-06

    申请号：US18571739

    申请日：2023-01-03

    申请人： SOUTHEAST UNIVERSITY

    发明人： Peng Cao ,  Guoqing He ,  Tai Yang

    IPC分类号： G06F30/3315 ,  G06F119/12

    CPC分类号： G06F30/3315 ,  G06F2119/12

    摘要： A post-routing path delay prediction method for a digital integrated circuit is provided. First, physical design and static timing analysis are performed on a circuit by a commercial physical design tool and a static timing analysis tool, timing and physical information of a path is extracted before routing of the circuit to be used as input features of a prediction model, then the timing and physical correlation of all stages of cells in the path is captured by a transformer network, a predicted post-routing path delay is calibrated by a residual prediction structure, and finally, a final predicted post-routing path delay is output.

    Method for predicting fluctuation of circuit path delay on basis of machine learning
    10.
    发明授权
    Method for predicting fluctuation of circuit path delay on basis of machine learning 有权

    公开(公告)号：US12112243B2

    公开(公告)日：2024-10-08

    申请号：US17043715

    申请日：2019-03-12

    申请人： Southeast University

    发明人： Peng Cao ,  Bingqian Xu ,  Jingjing Guo ,  Mengxiao Li ,  Jun Yang

    IPC分类号： G06N20/00 ,  G01R31/28

    CPC分类号： G06N20/00 ,  G01R31/2882

    摘要： A method for predicting the fluctuation of circuit path delay on the basis of machine learning, comprising the following steps: S1: selecting suitable sample characteristics by means of analyzing the relationship between circuit characteristics and path delay; S2: generating a random path by means of enumerating values of randomized parameters, acquiring the maximum path delay by means of performing Monte Carlo simulation on the random path, selecting a reliable path by means of the 3σ standard, and using the sample characteristics and path delay of the reliable path as a sample set (D); S3: establishing a path delay prediction model, and adjusting parameters of the model; S4: verifying the precision and stability of the path delay prediction model; S5: obtaining the path delay. The method for predicting the fluctuation of circuit path delay on the basis of machine learning has the advantages of high precision and low running time, thereby having remarkable advantages in the accuracy and efficiency of timing analysis.