公开(公告)号：US10970192B2

公开(公告)日：2021-04-06

申请号：US16368742

申请日：2019-03-28

Applicant: STMICROELECTRONICS (BEIJING) R&D CO. LTD

Inventor： Xiao Kang Jiao ,  PengFei Zhu

IPC: G06F11/00 ,  G06F11/36 ,  G06F11/22

Abstract: A debug-enabled processing device includes a processor, a communication transceiver circuit, and a debug support unit. The debug support unit has a plurality of dedicated debug registers to facilitate debugging a software program under execution by the processor. One of the plurality of debug registers is a control register having at least four bits, which are used to enable/disable a plurality of debugging operations. Others of the debug registers include a set of index registers that may be configured to pass data to and from the processor.

公开(公告)号：US10296441B2

公开(公告)日：2019-05-21

申请号：US15203659

申请日：2016-07-06

Applicant: STMicroelectronics (Beijing) R&D Co. Ltd

Inventor： Xiao Kang Jiao ,  PengFei Zhu

IPC: G06F11/00 ,  G06F11/36 ,  G06F11/22

Abstract: A debug-enabled processing device includes a processor, a communication transceiver circuit, and a debug support unit. The debug support unit has a plurality of dedicated debug registers to facilitate debugging a software program under execution by the processor. One of the plurality of debug registers is a control register having at least four bits, which are used to enable/disable a plurality of debugging operations. Others of the debug registers include a set of index registers that may be configured to pass data to and from the processor.

公开(公告)号：US10114644B2

公开(公告)日：2018-10-30

申请号：US15220338

申请日：2016-07-26

Applicant: STMicroelectronics (Beijing) R&D Co. Ltd

Inventor： PengFei Zhu ,  Xiao Kang Jiao

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/32

Abstract: A decoding logic method is arranged to execute a zero-overhead loop in an embedded digital signal processor (DSP). In the method, instruction data is fetched from a memory, and a plurality of instruction tokens, which are derived from the instruction data, are stored in a token buffer. A first portion of one or more instruction tokens from the token buffer are passed to a first decode module, which may be an instruction decode module, and a second portion of the one or more instruction tokens from the token buffer are passed to a second decode module, which may be a loop decode module. The second decode module detects a special loop instruction token, and based on the detection of the special loop instruction token, a loop counter is conditionally tested. Using the first decode module, at least one instruction token of an iterative algorithm is assembled into a single instruction, which is executable in a single execution cycle. Based on the conditional test of the loop counter, the first decode module further assembles a loop branch instruction of the iterative algorithm into the single instruction executable in one execution cycle.