公开(公告)号：US20170205461A1

公开(公告)日：2017-07-20

申请号：US15324851

申请日：2015-05-28

Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Jean-Marc DAVEAU ,  Philippe ROCHE ,  Didier FUIN

IPC: G01R31/3177 ,  G01R31/317

CPC classification number: G01R31/3177 ,  G01R31/31701 ,  G01R31/31723 ,  G01R31/31724 ,  G01R31/318555

Abstract: A device may include a control circuit configured to place, after a normal mode operation of N flip-flops, the N flip-flops in a test mode in which the test input of the first flip-flop of the chain is intended to receive a first sequence of test bits. A memory may be configured to store a sequence of N values delivered by the test output of the last flip-flop of the chain. The control circuit may be configured to deliver, at the test input of the first flip-flop of the chain, the sequence of N stored values to restore the state of the N flip-flops before their placement in the test mode.

公开(公告)号：US20150377962A1

公开(公告)日：2015-12-31

申请号：US14662530

申请日：2015-03-19

Applicant: STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Jean-Marc DAVEAU ,  Sylvain CLERC ,  Philippe ROCHE

IPC: G01R31/3177

CPC classification number: G01R31/3177 ,  G01R31/318502 ,  G06F11/183 ,  G06F11/267

Abstract: A method for managing operation of a logic component is provided, with the logic component including a majority vote circuit and an odd number of flip-flops equal to at least three. The method includes, following a normal operating mode of the logic component, placing a flip-flop in a test mode, and injecting a test signal into a test input of the flip-flop being tested while a logic state of the other flip-flops is frozen. A test signal output is analyzed. At the end of the test, the logic component is placed back in the normal operating mode. The majority vote circuit restores a value of the output signal from the logic component that existed prior to initiation of the test.

Abstract translation: 提供了一种用于管理逻辑部件的操作的方法，其中逻辑部件包括等于至少三个的多数投票电路和奇数触发器。 该方法包括：遵循逻辑部件的正常操作模式，将触发器置于测试模式，并将测试信号注入被测试的触发器的测试输入，而其它触发器的逻辑状态 被冻结。 分析测试信号输出。 在测试结束时，将逻辑组件放回正常操作模式。 多数投票电路恢复来自在开始测试之前存在的逻辑组件的输出信号的值。