公开(公告)号：US20180335526A1

公开(公告)日：2018-11-22

申请号：US15981321

申请日：2018-05-16

Applicant: STMicroelectronics (Crolles 2) SAS ,  Centre National De La Recherche Scientifique ,  UNIVERSITE D'AIX MARSEILLE ,  UNIVERSITE DE TOULON

Inventor： Martin COCHET ,  Dimitri SOUSSAN ,  Fady ABOUZEID ,  Gilles GASIOT ,  Philippe ROCHE

IPC: G01T1/02 ,  H03K3/03

CPC classification number: G01T1/026

Abstract: Absorbed ionizing particles differentially effect first and second acquiring circuit stages configured to respectively generate first and second acquisition signals. Each acquisition signal has a characteristic that is variable as a function of an amount of absorbed ionizing particles. A measuring circuit generates, on the basis of the first and second acquisition signals, a relative parameter indicative of a relationship between the variable characteristics. A computation of a total ionizing dose is made using a 1st- or 2nd-degree polynomial relationship in the relative parameter.

公开(公告)号：US20230299009A1

公开(公告)日：2023-09-21

申请号：US18120555

申请日：2023-03-13

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Fady ABOUZEID ,  Philippe ROCHE

IPC: H01L23/538 ,  H01L21/768

CPC classification number: H01L23/5386 ,  H01L23/5385 ,  H01L21/76864

Abstract: An electronic device includes a first electronic chip, a second electronic chip, and an interconnection circuit. A first region of a first surface of the first electronic chip is assembled by hybrid bonding to a third region of a third surface of the interconnection circuit. A second region of a second surface of the second electronic chip is assembled by hybrid to a fourth region of the third surface of the interconnection circuit. In this configuration, the first electronic chip is electrically coupled to the second electronic chip through the interconnection circuit. The first surface of the first electronic chip further includes a fifth region which is not in contact with the interconnection circuit. This fifth region includes a connection pad electrically connected by a connection element to a connection substrate to which the interconnection circuit is mounted.

公开(公告)号：US20170205461A1

公开(公告)日：2017-07-20

申请号：US15324851

申请日：2015-05-28

Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Jean-Marc DAVEAU ,  Philippe ROCHE ,  Didier FUIN

IPC: G01R31/3177 ,  G01R31/317

CPC classification number: G01R31/3177 ,  G01R31/31701 ,  G01R31/31723 ,  G01R31/31724 ,  G01R31/318555

Abstract: A device may include a control circuit configured to place, after a normal mode operation of N flip-flops, the N flip-flops in a test mode in which the test input of the first flip-flop of the chain is intended to receive a first sequence of test bits. A memory may be configured to store a sequence of N values delivered by the test output of the last flip-flop of the chain. The control circuit may be configured to deliver, at the test input of the first flip-flop of the chain, the sequence of N stored values to restore the state of the N flip-flops before their placement in the test mode.

公开(公告)号：US20200252059A1

公开(公告)日：2020-08-06

申请号：US16747341

申请日：2020-01-20

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA

Inventor： Capucine LECAT-MATHIEU DE BOISSAC ,  Fady ABOUZEID ,  Gilles GASIOT ,  Philippe ROCHE ,  Victor MALHERBE

IPC: H03K5/14 ,  H03K5/135

Abstract: A first circuit includes a first chain of identical stages defining first and second delay lines. A second circuit includes a second chain of identical stages defining third and fourth delay lines. The stages of the second chain are identical to the stages of the first chain. A third circuit selectively couples one of the third delay line, the fourth delay line, or a first input of the third circuit to an input of the first circuit.

公开(公告)号：US20150377962A1

公开(公告)日：2015-12-31

申请号：US14662530

申请日：2015-03-19

Applicant: STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Jean-Marc DAVEAU ,  Sylvain CLERC ,  Philippe ROCHE

IPC: G01R31/3177

CPC classification number: G01R31/3177 ,  G01R31/318502 ,  G06F11/183 ,  G06F11/267

Abstract: A method for managing operation of a logic component is provided, with the logic component including a majority vote circuit and an odd number of flip-flops equal to at least three. The method includes, following a normal operating mode of the logic component, placing a flip-flop in a test mode, and injecting a test signal into a test input of the flip-flop being tested while a logic state of the other flip-flops is frozen. A test signal output is analyzed. At the end of the test, the logic component is placed back in the normal operating mode. The majority vote circuit restores a value of the output signal from the logic component that existed prior to initiation of the test.

Abstract translation: 提供了一种用于管理逻辑部件的操作的方法，其中逻辑部件包括等于至少三个的多数投票电路和奇数触发器。 该方法包括：遵循逻辑部件的正常操作模式，将触发器置于测试模式，并将测试信号注入被测试的触发器的测试输入，而其它触发器的逻辑状态 被冻结。 分析测试信号输出。 在测试结束时，将逻辑组件放回正常操作模式。 多数投票电路恢复来自在开始测试之前存在的逻辑组件的输出信号的值。