公开(公告)号：US20170064321A1

公开(公告)日：2017-03-02

申请号：US14837051

申请日：2015-08-27

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Vindhyeshwari Kumar KASHYAP ,  Ajit Singh MOTRA ,  Mahesh Narain SHUKLA ,  Tarun SINGAL

IPC: H04N19/44 ,  H04N19/85 ,  H04N19/423 ,  H04N19/436

CPC classification number: H04N19/436 ,  H04N19/91

Abstract: A video decoder includes an input configured to receive a plurality of bins of a video digital data stream to be decoded. A processor and a memory associated therewith are configured to perform parallel decoding of multiple bins of the plurality of bins in a given processing cycle based upon a table containing delta range values and probable symbols.

Abstract translation: 视频解码器包括被配置为接收待解码的视频数字数据流的多个存储槽的输入。 处理器和与其相关联的存储器被配置为基于包含增量范围值和可能符号的表，在给定处理周期内执行多个箱中的多个箱的并行解码。