公开(公告)号：US20190197014A1

公开(公告)日：2019-06-27

申请号：US15850535

申请日：2017-12-21

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Tejinder KUMAR ,  Rathod RONAK KISHORBHAI ,  Apurva SEN ,  Rakesh MALIK

IPC: G06F15/78 ,  G06F17/30

Abstract: Various embodiments provide a content addressable memory (CAM) architecture that utilizes non-bit addressable memory, such as a single or dual port random access memory. The CAM includes a first non-bit addressable memory, a second non-bit addressable memory, a multiplexer, a write operation encoder, a read operation encoder, and a match signal generator. In contrast to bit addressable memories, non-bit addressable memories are widely available, have high performance frequency, and are area efficient as compared to bit addressable memories. Accordingly, the CAM architecture described herein has low costs and time to market, increased processing time, and improved area efficiency.