公开(公告)号：US20190128960A1

公开(公告)日：2019-05-02

申请号：US15797504

申请日：2017-10-30

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Tejinder KUMAR ,  Akshat JAIN

IPC: G01R31/317 ,  G01R31/3177

Abstract: Various embodiments provide a parallel checker to determine whether a device under test (DUT) is functioning properly or outputting erroneous bits. A test pattern or test data is injected into the DUT, and the parallel checker compares output data of the DUT to expected data stored in the parallel checker. The parallel checker determines an error in the event that a bit in the output data does not match in the expected data. The parallel checker is independent of test pattern length and data width at the parallel input of the parallel checker. Accordingly, the parallel checker may be used for multiple different test patterns, such as a PRBS 7, a CJTPAT, CRPAT, etc. Further, the parallel checker provides high-speed synchronization between data received from the DUT and expected test data stored in the parallel checker. In addition, the parallel checker consumes relatively low power and chip area in, for example, a SoC environment.

公开(公告)号：US20190197014A1

公开(公告)日：2019-06-27

申请号：US15850535

申请日：2017-12-21

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Tejinder KUMAR ,  Rathod RONAK KISHORBHAI ,  Apurva SEN ,  Rakesh MALIK

IPC: G06F15/78 ,  G06F17/30

Abstract: Various embodiments provide a content addressable memory (CAM) architecture that utilizes non-bit addressable memory, such as a single or dual port random access memory. The CAM includes a first non-bit addressable memory, a second non-bit addressable memory, a multiplexer, a write operation encoder, a read operation encoder, and a match signal generator. In contrast to bit addressable memories, non-bit addressable memories are widely available, have high performance frequency, and are area efficient as compared to bit addressable memories. Accordingly, the CAM architecture described herein has low costs and time to market, increased processing time, and improved area efficiency.