公开(公告)号：US20040174752A1

公开(公告)日：2004-09-09

申请号：US10701115

申请日：2003-11-04

Applicant: STMICROELECTRONICS S.A.

Inventor： Bernard Ramanadin

IPC: G11C007/00

CPC classification number: G11C7/1054 ,  G06F5/00 ,  G06F13/4072 ,  G11C7/1051 ,  G11C7/106

Abstract: An output buffer register includes a first input flip-flop register receiving a given number N of input signals, a latching register, a selection register, and an output multiplexer delivering N output signals. Only one data input of the enable register receives an enable signal. In this way, the propagation time at the input of the buffer register is reduced.

Abstract translation: 输出缓冲寄存器包括接收给定数量N个输入信号的第一输入触发器寄存器，锁存寄存器，选择寄存器和输出N个输出信号的输出多路复用器。 使能寄存器只有一个数据输入端接收使能信号。 以这种方式，缓冲寄存器的输入端的传播时间减少。

公开(公告)号：US20040193836A1

公开(公告)日：2004-09-30

申请号：US10701384

申请日：2003-11-04

Applicant: STMICROELECTRONICS S.A.

Inventor： Bernard Ramanadin

IPC: G06F015/00

CPC classification number: G06F13/385

Abstract: A resynchronization module for use in an electronic system comprising a system bus comprises pipeline means of for pipelining the transactions intended for and/or originating from the associated functional module. The pipeline means comprise a first buffer circuit and at least one second buffer circuit, which are connected in parallel, and are each, adapted for storing transaction data of a specific transaction.

Abstract translation: 用于包括系统总线的电子系统的再同步模块包括用于流水线化用于和/或源自相关联的功能模块的事务的流水线装置。 流水线装置包括并联连接的第一缓冲电路和至少一个第二缓冲电路，并且各自适于存储特定事务的交易数据。