公开(公告)号：US20240048144A1

公开(公告)日：2024-02-08

申请号：US18352581

申请日：2023-07-14

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Matteo QUARTIROLI ,  Alessandro MECCHIA ,  Paolo PESENTI

IPC: H03L7/081 ,  H03L7/099

CPC classification number: H03L7/0814 ,  H03L7/0992

Abstract: A device includes a local oscillator, an all-digital phase-locked loop, a digital signal generator, sampling circuitry, and an interface. The local oscillator generates a local clock signal. The all-digital phase locked loop generates a sampling control signal. The ADPLL includes a phase-error detector, a digital filter and a sigma-delta modulator. The phase detector generates a phase error signal based on a loop clock signal and a received reference signal. The digital filter generates a signal indicative of a frequency ratio between a frequency of the reference clock signal and the local clock frequency based on the phase error signal. The sigma-delta modulator generates a modulated signal based on the signal indicative of the frequency ratio. The sampling control signal is based on the modulated signal. The sampling circuitry samples digital signals generated by the digital signal generator at a sampling frequency, which is a function of the sampling control signal.

公开(公告)号：US20220315416A1

公开(公告)日：2022-10-06

申请号：US17707454

申请日：2022-03-29

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Matteo QUARTIROLI ,  Alessandro MECCHIA ,  Laura MAESTRI

IPC: B81B7/02 ,  G01D5/244

Abstract: The sensor is configured to provide a digital output signal and has a digital detector, which is configured to detect a physical quantity and generate a conditioned digital signal indicative of the detected physical quantity; and a rate modification stage, configured to receive the conditioned digital signal and a group of parameters, the group of parameters comprising an interpolation factor and a downsampling factor, and to provide the digital output signal. The rate modification stage has an interpolator and a decimation element. The interpolator is configured to receive and to upsample the conditioned digital signal based on the interpolation factor and to provide an interpolated signal. The decimation element is configured to downsample the interpolated signal based on the downsampling factor, thereby generating the digital output signal.