公开(公告)号：US20040229454A1

公开(公告)日：2004-11-18

申请号：US10781565

申请日：2004-02-18

Applicant: STMICROELECTRONICS SA ,  KONINKLIJKE PHILIPS ELECTRONICS N.V.

Inventor： Joaquin Torres ,  Vincent Arnal ,  Laurent Gosset

IPC: H01L021/76

CPC classification number: H01L23/5329 ,  H01L21/7682 ,  H01L23/5222 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A process for fabricating an integrated electronic circuit comprises the formation of at least one air gap between interconnect elements above only a defined portion of a surface of a substrate, within an interconnect layer. The interconnect layer comprises a sacrificial material and extends beneath an intermediate layer of permeable material. The air gap is formed by removal, through the intermediate layer, of at least part of the sacrificial material by bringing the permeable material into contact with an agent for removing the sacrificial material, to which agent the permeable material is resistant.

Abstract translation: 一种用于制造集成电子电路的工艺包括在互连层内形成位于衬底表面的限定部分之上的互连元件之间的至少一个气隙。 互连层包括牺牲材料并在可渗透材料的中间层之下延伸。 通过使可渗透​​材料与用于除去牺牲材料的试剂接触而将可渗透材料抵抗的试剂与通过中间层去除至少部分牺牲材料形成气隙。