公开(公告)号：US20230359368A1

公开(公告)日：2023-11-09

申请号：US18192237

申请日：2023-03-29

Applicant: STMicroelectronics(Rousset) SAS

Inventor： Mark Wallis ,  Laurent Lestringand

IPC: G06F3/06

CPC classification number: G06F3/0622 ,  G06F3/0637 ,  G06F3/0673

Abstract: In accordance with an embodiment, a system-on-chip includes: a memory circuit comprising a first memory region accessible with a first access right level and a second memory region accessible with the first access right level or a second access right level, at least one first peripheral having the first access right level, at least one second peripheral having the second access right level; and a direct memory access circuit configured to generate direct memory accesses, wherein the direct memory access circuit includes at least one first direct memory access controller having the first access right level and at least one second direct memory access controller having the second access right level.

公开(公告)号：US11386037B2

公开(公告)日：2022-07-12

申请号：US16684296

申请日：2019-11-14

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Emmanuel Ardichvili ,  Laurent Lestringand ,  Patrick Valdenaire

IPC: G06F15/78 ,  G06F15/173 ,  G06F21/62 ,  G06F13/14

Abstract: A system includes a plurality of items of master equipment, each having a programing interface, and a plurality of slave equipment. An interconnect circuit is coupled between the items of master equipment and the items of slave equipment. Each transaction is assigned an attribute capable of taking on at least two attribute values corresponding to at least two states for the master equipment. Each item of slave equipment is associated with an identifier capable of taking on at least two values corresponding respectively to at least two properties for the slave equipment. Each item of master equipment automatically inherits the property of its programing interface. A filtering circuit is configured to, in the presence of a transaction intended for an item of slave equipment, compare the corresponding attribute value with an identifier value of the intended slave equipment and reject or not reject the transaction based on the comparison.

公开(公告)号：US20200174964A1

公开(公告)日：2020-06-04

申请号：US16684296

申请日：2019-11-14

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Emmanuel Ardichvili ,  Laurent Lestringand ,  Patrick Valdenaire

IPC: G06F15/78 ,  G06F21/62 ,  G06F15/173

Abstract: A system includes a plurality of items of master equipment, each having a programing interface, and a plurality of slave equipment. An interconnect circuit is coupled between the items of master equipment and the items of slave equipment. Each transaction is assigned an attribute capable of taking on at least two attribute values corresponding to at least two states for the master equipment. Each item of slave equipment is associated with an identifier capable of taking on at least two values corresponding respectively to at least two properties for the slave equipment. Each item of master equipment automatically inherits the property of its programing interface. A filtering circuit is configured to, in the presence of a transaction intended for an item of slave equipment, compare the corresponding attribute value with an identifier value of the intended slave equipment and reject or not reject the transaction based on the comparison.