公开(公告)号：US20030217227A1

公开(公告)日：2003-11-20

申请号：US10146537

申请日：2002-05-14

Applicant: STMicroelectronics, Inc.

Inventor： Sivagnanam Parthasarathy ,  Alessandro Risso

IPC: G06F012/00

CPC classification number: G06F9/328 ,  G06F8/66 ,  G06F9/3004 ,  G06F9/30087 ,  G06F12/126

Abstract: A ROM patching apparatus for use in a data processing system that executes instruction code stored the ROM. The ROM patching apparatus comprises: 1) a patch buffer for storing a first replacement cache line containing a first new instruction suitable for replacing at least a portion of the code in the ROM; 2) a lockable cache; 3) core processor logic operable to read from an associated memory a patch table containing a first table entry, the first table entry containing 1) the first new instruction and 2) a first patch address identifying a first patched ROM address of the at least a portion of the code in the ROM. The core processor logic loads the first new instruction from the patch table into the patch buffer, stores the first replacement cache line from the patch buffer into the lockable cache, and locks the first replacement cache line into the lockable cache.

Abstract translation: 一种ROM修补装置，用于执行存储ROM的指令代码的数据处理系统。 ROM修补装置包括：1）补丁缓冲器，用于存储包含适于替换ROM中的代码的至少一部分的第一新指令的第一替换高速缓存行; 2）可锁定缓存; 3）核心处理器逻辑，可操作以从相关联的存储器读取包含第一表项的修补表，所述第一表条目包含1）所述第一新指令;以及2）第一补丁地址，其标识所述至少一个 部分ROM中的代码。 核心处理器逻辑将补丁表中的第一个新指令加载到补丁缓冲区中，将补丁缓冲区中的第一个替换高速缓存行存储到可锁定高速缓存中，并将第一个替换高速缓存行锁定到可锁定高速缓存中。