公开(公告)号：US20040073749A1

公开(公告)日：2004-04-15

申请号：US10270753

申请日：2002-10-15

Applicant: STMICROELECTRONICS, INC. ,  STMICROELECTRONICS, S.A.

Inventor： Sivagnanam Parthasarathy ,  Andrew Cofler ,  Lionel Chaverot

IPC: G06F012/00

CPC classification number: G06F9/381 ,  G06F9/30181 ,  G06F9/325 ,  G06F9/3875 ,  G06F12/0864 ,  G06F12/0877 ,  G06F2212/1028 ,  Y02D10/13

Abstract: For instruction clusters for which no significant performance penalty is incurred, such as execution of hardware loops, a processor automatically and dynamically switches to a pipelined two-cycle access to an associated associative cache rather than a single-cycle access. An access involving more than one cycle uses less power because only the hit way within the cache memory is accessed rather than all ways within the indexed cache line. To maintain performance, the single-cycle cache access is utilized in all remaining instructions. In addition, where instruction clusters within a hardware loop fit entirely within a pre-fetch buffer, the cache sub-system is idled for any remaining iterations of the hardware loop to further reduce power consumption.

Abstract translation: 对于不会产生显着性能损失（如执行硬件循环）的指令集，处理器自动和动态切换到流水线的两周期访问关联的关联高速缓存而不是单周期访问。 涉及多个周期的访问使用更少的功率，因为​​只有高速缓存中的命中方式被访问，而不是索引的高速缓存行内的所有方式。 为了保持性能，在所有剩余指令中使用单周期高速缓存访​​问。 此外，在硬件环路内的指令集合完全适合预取缓冲器的情况下，高速缓存子系统对于硬件循环的任何剩余迭代都是空闲的，以进一步降低功耗。

公开(公告)号：US20040098563A1

公开(公告)日：2004-05-20

申请号：US10299120

申请日：2002-11-19

Applicant: STMICROELECTRONICS, INC.

Inventor： Sivagnanam Parthasarathy ,  Alexander Driker

IPC: G06F015/00

CPC classification number: G06F9/3885 ,  G06F9/30043 ,  G06F9/30072

Abstract: A processor architecture supports an electrical interface for coupling the processor core to one or more coprocessor extension units executing computational instructions, with a split-instruction transaction employed to provide operands and instructions to an extension unit and retrieve results from the extension unit. The generic instructions for sending an operation and data to the extension unit and/or retrieving data from the extension unit allow new computational instructions to be introduced without regeneration of the processor architecture. Support for multiple extension units and/or multiple execution pipes within each extension unit, multi-cycle execution latencies and different execution latencies between or within extension units, extension unit instruction predicates, and for handling processor core stalls and result save/restore on interrupt is included.

Abstract translation: 处理器架构支持用于将处理器核心耦合到执行计算指令的一个或多个协处理器扩展单元的电接口，其中分配指令事务用于向扩展单元提供操作数和指令，并从扩展单元检索结果。 用于向扩展单元发送操作和数据和/或从扩展单元检索数据的通用指令允许在不重新生成处理器架构的情况下引入新的计算指令。 支持每个扩展单元内的多个扩展单元和/或多个执行管道，多周期执行延迟和扩展单元之间或扩展单元指令谓词之间的不同执行延迟，以及用于处理中断的处理器内核停止和结果保存/恢复 包括。

公开(公告)号：US20030217227A1

公开(公告)日：2003-11-20

申请号：US10146537

申请日：2002-05-14

Applicant: STMicroelectronics, Inc.

Inventor： Sivagnanam Parthasarathy ,  Alessandro Risso

IPC: G06F012/00

CPC classification number: G06F9/328 ,  G06F8/66 ,  G06F9/3004 ,  G06F9/30087 ,  G06F12/126

Abstract: A ROM patching apparatus for use in a data processing system that executes instruction code stored the ROM. The ROM patching apparatus comprises: 1) a patch buffer for storing a first replacement cache line containing a first new instruction suitable for replacing at least a portion of the code in the ROM; 2) a lockable cache; 3) core processor logic operable to read from an associated memory a patch table containing a first table entry, the first table entry containing 1) the first new instruction and 2) a first patch address identifying a first patched ROM address of the at least a portion of the code in the ROM. The core processor logic loads the first new instruction from the patch table into the patch buffer, stores the first replacement cache line from the patch buffer into the lockable cache, and locks the first replacement cache line into the lockable cache.

Abstract translation: 一种ROM修补装置，用于执行存储ROM的指令代码的数据处理系统。 ROM修补装置包括：1）补丁缓冲器，用于存储包含适于替换ROM中的代码的至少一部分的第一新指令的第一替换高速缓存行; 2）可锁定缓存; 3）核心处理器逻辑，可操作以从相关联的存储器读取包含第一表项的修补表，所述第一表条目包含1）所述第一新指令;以及2）第一补丁地址，其标识所述至少一个 部分ROM中的代码。 核心处理器逻辑将补丁表中的第一个新指令加载到补丁缓冲区中，将补丁缓冲区中的第一个替换高速缓存行存储到可锁定高速缓存中，并将第一个替换高速缓存行锁定到可锁定高速缓存中。

公开(公告)号：US20030135530A1

公开(公告)日：2003-07-17

申请号：US10032742

申请日：2001-10-22

Applicant: STMicroelectronics, Inc.

Inventor： Sivagnanam Parthasarathy ,  Cinzia A. Bartolommei

IPC: G06F007/00

CPC classification number: G06F7/724

Abstract: A flexible Galois Field multiplier is provided which implements multiplication of two elements within a finite field defined by a degree and generator polynomial. One preferred embodiment provides a method for multiplying two elements of a finite field. According to the method, two input operands are mapped into a composite finite field, an initial KOA processing is performed upon the two operands in order to prepare the two operands for a multiplication in the ground field, the multiplication in the ground field is performed through the use of a triangular basis multiplier, and final KOA3 processing and optional modulo reduction processing is performed to produce the result. This design allows rapid redefinition of the degree and generator polynomial used for the ground field and the extension field.

Abstract translation: 提供了一种灵活的伽罗瓦域乘法器，其实现了由度和生成多项式定义的有限域内的两个元素的乘法。 一个优选实施例提供了一种用于将有限域的两个元素相乘的方法。 根据该方法，将两个输入操作数映射到复合有限域中，对两个操作数执行初始KOA处理，以便为地面场中的乘法准备两个操作数，地面场中的乘法通过 执行三角形基乘法器的使用以及最终的KOA3处理和可选的模减缩处理以产生结果。 该设计允许对用于地面场和扩展场的度数和生成多项式进行快速重新定义。