公开(公告)号：US20170220443A1

公开(公告)日：2017-08-03

申请号：US15253002

申请日：2016-08-31

Applicant: STMicroelectronics (Alps) SAS

Inventor： Mickael Broutin ,  Benoit Lelievre ,  Nicolas Anquet

IPC: G06F11/27 ,  G06F11/07

CPC classification number: G06F11/27 ,  G06F11/0778 ,  G11C7/24 ,  G11C29/12 ,  G11C2029/3602

Abstract: Embodiments of the circuits described include a method wherein at least one command signal is activated. The activation of the at least one command signal causes a request to a testing circuit of a memory array to enter a memory test mode. The requested memory test mode permits at least part of the memory array to be read. In response to activation of the at least one command signal, a test control circuit initiates an overwrite sequence to overwrite the data stored in the memory array. The test control circuit enables the memory test mode once the overwrite sequence has been completed.

公开(公告)号：US10331530B2

公开(公告)日：2019-06-25

申请号：US15253002

申请日：2016-08-31

Applicant: STMicroelectronics (Alps) SAS

Inventor： Mickael Broutin ,  Benoit Lelievre ,  Nicolas Anquet

IPC: G06F11/00 ,  G06F11/27 ,  G06F11/07 ,  G11C7/24 ,  G11C29/12 ,  G11C29/36

Abstract: Embodiments of the circuits described include a method wherein at least one command signal is activated. The activation of the at least one command signal causes a request to a testing circuit of a memory array to enter a memory test mode. The requested memory test mode permits at least part of the memory array to be read. In response to activation of the at least one command signal, a test control circuit initiates an overwrite sequence to overwrite the data stored in the memory array. The test control circuit enables the memory test mode once the overwrite sequence has been completed.