公开(公告)号：US12112831B2

公开(公告)日：2024-10-08

申请号：US17877592

申请日：2022-07-29

Applicant: Micron Technology, Inc.

Inventor： Bryan David Kerstetter ,  Alan J. Wilson ,  Donald Martin Morgan

IPC: G11C8/20 ,  G11C7/10 ,  G11C7/24

CPC classification number: G11C7/24 ,  G11C7/1063 ,  G11C7/1066 ,  G11C8/20

Abstract: Methods, systems, and devices for memory row-hammer mitigation are described. A memory device may operate based on a scheme that is continuous across power cycles. For example, the memory device may access a region if a value of a counter does not satisfy a threshold value and may access the region if a value of the counter satisfies the threshold value. Upon transitioning power states, the value of the counter may be stored to a non-volatile memory such that it may be accessed when transitioning back to the original power state (e.g., an “ON” state). Accordingly, the value of the counter may be maintained across power cycles.

公开(公告)号：US12016094B2

公开(公告)日：2024-06-18

申请号：US18154907

申请日：2023-01-16

Applicant: Lutron Technology Company LLC

Inventor： Russell Weightman ,  Jonathan T. Lenz ,  Jaykrishna A. Shukla ,  Daniel Curtis Raneri

IPC: H05B39/08 ,  G11C5/00 ,  G11C5/02 ,  G11C7/04 ,  G11C7/24 ,  G11C11/406 ,  G11C29/12 ,  H05B39/04 ,  H05B47/10 ,  H05B47/165 ,  H05B47/17 ,  H05B47/185

CPC classification number: H05B39/086 ,  G11C5/005 ,  G11C5/025 ,  G11C7/04 ,  G11C7/24 ,  G11C11/40626 ,  G11C29/12 ,  H05B39/04 ,  H05B47/10 ,  H05B47/165 ,  H05B47/17 ,  H05B47/185

Abstract: A load control device may include a semiconductor switch, a control circuit, and first and second terminals adapted to be coupled to a remote device. The load control device may include a first switching circuit coupled to the second terminal, and a second switching circuit coupled between the first terminal and the second terminal. The control circuit may be configured to render the first switching circuit conductive to conduct a charging current from an AC power source to a power supply of the remote device during a first time period of a half-cycle of the AC power source, and further configured to render the first and second switching circuits conductive and non-conductive to communicate with the remote device via the second terminal during a second time period of the half-cycle of the AC power source.

公开(公告)号：US20240194231A1

公开(公告)日：2024-06-13

申请号：US18531543

申请日：2023-12-06

Applicant: Rambus Inc.

Inventor： Taeksang Song ,  Evan Lawrence Erickson ,  Steven C. Woo

IPC: G11C7/10 ,  G11C7/24

CPC classification number: G11C7/1069 ,  G11C7/1039 ,  G11C7/1063 ,  G11C7/24

Abstract: A buffer integrated circuit (IC) chip is disclosed. The buffer IC chip includes host interface circuitry to receive a read command to retrieve read data from a memory. Memory interface circuitry couples to the memory. Data freshness authentication circuitry performs a freshness verification operation on the read data. Read data forwarding circuitry, in a skid mode of operation, transmits the read data to the host prior to completion of the freshness verification operation.

公开(公告)号：US20240177753A1

公开(公告)日：2024-05-30

申请号：US18432390

申请日：2024-02-05

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Jae-Mun OH

IPC: G11C7/24

CPC classification number: G11C7/24

Abstract: Disclosed herein is an apparatus for hardware metering using a memory-type camouflaged cell. The apparatus includes memory including at least one camouflaged memory cell in which a key is hidden by a designer in advance and a controller for controlling whether to block the supply of power to the memory. The controller may perform reading a key from a corresponding key location in the multiple memory cells of the memory based on key location information stored in the controller when a key is input from the outside, determining whether the key input from the outside is the same as the key read from the memory, setting an authentic flag based on the determination result, and performing control based on the set authentic flag such that the memory operates normally or the supply of power is blocked.

公开(公告)号：US20240161800A1

公开(公告)日：2024-05-16

申请号：US18056158

申请日：2022-11-16

Applicant: NVIDIA Corp.

Inventor： Mahmut Ersin Sinangil ,  Sudhir Shrikantha Kudva ,  Nikola Nedovic ,  Carl Thomas Gray

IPC: G11C7/24 ,  G11C7/10 ,  G11C7/20

CPC classification number: G11C7/24 ,  G11C7/1063 ,  G11C7/20

Abstract: PUF cells utilizing a dual-interlocking scheme demonstrating improved noise immunity and stability across different V/T conditions and different uses over time in noisy environments. The PUF cell may be advantageously utilized in conjunction with error detection techniques that screen out unstable cells. A set of such PUF cells utilized to generate a device-specific bit pattern, for example a master key.

公开(公告)号：US11961567B2

公开(公告)日：2024-04-16

申请号：US17848409

申请日：2022-06-24

Applicant: PUFsecurity Corporation

Inventor： Kai-Hsin Chuang ,  Chi-Yi Shao ,  Chun-Heng You

IPC: G11C11/4078 ,  G11C7/24 ,  G11C11/412 ,  G11C16/10 ,  G11C16/22 ,  G11C16/26 ,  G11C16/34

CPC classification number: G11C16/22 ,  G11C7/24 ,  G11C11/4078 ,  G11C11/412 ,  G11C16/102 ,  G11C16/26 ,  G11C16/3404

Abstract: A key storage device comprising a first key unit and a second key unit is disclosed. The first key unit is configured to output a first logic value through, comprising: a first setting circuit configured to output a first setting voltage; and a first inverter comprising a first output transistor having a first threshold voltage, configured to receive the first setting voltage and generate the first logic value. The second key unit is configured to output a second logic value through a second node, comprising: a second setting circuit configured to output a second setting voltage; and a second inverter comprising a second output transistor having a second threshold voltage, configured to receive the second setting voltage and generate the second logic value. The absolute value of first threshold voltage is lower than which of the second threshold voltage. The first setting voltage is higher than the second setting voltage.

公开(公告)号：US11868172B2

公开(公告)日：2024-01-09

申请号：US17566926

申请日：2021-12-31

Applicant: Renesas Electronics America Inc.

Inventor： Zhihan Zhang ,  Yuan Zhang

IPC: G11C8/00 ,  G06F1/06 ,  G06F1/10 ,  G06F1/12 ,  G11C7/24 ,  G11C7/22

CPC classification number: G06F1/06 ,  G06F1/10 ,  G06F1/12 ,  G11C7/22 ,  G11C7/24

Abstract: In an embodiment, an apparatus an apparatus including a memory module is described. The memory module can include a plurality of memory ranks and a register clock driver (RCD) coupled to the plurality of memory ranks. The RCD can include a receiver configured to receive a chip select signal for selecting one or more memory ranks. The RCD can further include a logic circuit coupled to the receiver, and an output driver coupled to the logic circuit. The RCD can further include a loopback circuit configured to sample the chip select signal from one or more of a first sampling point between the receiver and the logic circuit and a second sampling point between the logic circuit and the output driver.

公开(公告)号：US20230420020A1

公开(公告)日：2023-12-28

申请号：US17852344

申请日：2022-06-28

Applicant: MONTAGE TECHNOLOGY (KUNSHAN) CO., LTD.

Inventor： Yibo JIANG ,  Leechung YIU ,  Christopher COX ,  Robert Xi JIN ,  Lizhi JIN ,  Leonard DATUS

IPC: G11C7/24 ,  G11C7/02 ,  G11C7/10

CPC classification number: G11C7/24 ,  G11C7/02 ,  G11C7/1048 ,  G11C7/1063 ,  G11C7/109

Abstract: An apparatus for controlling access to a memory device comprising rows of memory units is provided. The apparatus comprises: an operation monitor configured to track memory operations to the rows of memory units of the memory device; a row hammer counter configured to determining, for each of the rows of memory units, row hammer effects experienced by the row of memory units due to the memory operations to the other rows of memory units of the memory device; a mitigation module configured to initiate, for each of the rows of memory units, row hammer mitigation in case that accumulated row hammer effects experienced by the row of memory units reach a predetermined threshold; and a virtual host module configured to perform the row hammer mitigation targeting a row of memory units in response to the initiation of row hammer mitigation for the row of memory units by the mitigation module.

公开(公告)号：US11842784B2

公开(公告)日：2023-12-12

申请号：US17548242

申请日：2021-12-10

Applicant: SK hynix Inc.

Inventor： Seung Woo Lee ,  Dong Hee Han

IPC: G11C7/00 ,  G11C29/50 ,  G11C11/4076 ,  G11C11/16 ,  G11C7/24

CPC classification number: G11C29/50 ,  G11C7/24 ,  G11C11/1675 ,  G11C11/4076

Abstract: A semiconductor device includes a test command generation circuit that generates a test write command and a test read command when entering a test mode, and an input/output control circuit that controls a memory block, the memory block including a plurality of banks such that write operations are simultaneously performed on the plurality of banks based on the test write command and read operations are simultaneously performed on the plurality of banks based on the test read command.

公开(公告)号：US11763890B2

公开(公告)日：2023-09-19

申请号：US17409584

申请日：2021-08-23

Applicant: KIOXIA CORPORATION

Inventor： Yuki Shimizu ,  Yoshihiko Kamata ,  Tsukasa Kobayashi ,  Hideyuki Kataoka ,  Koji Kato ,  Takumi Fujimoto ,  Yoshinao Suzuki ,  Yuui Shimizu

IPC: G11C16/30 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  G11C7/24 ,  G11C16/10 ,  G11C7/10 ,  G11C16/28

CPC classification number: G11C16/0483 ,  G11C7/109 ,  G11C7/24 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/28 ,  G11C16/30

Abstract: A semiconductor memory device includes a substrate, first and second P-type well regions on the substrate, an N-type well region on the substrate and sandwiched between the first and second P-type well regions, a first peripheral circuit on a region of the first P-type well region adjacent to the N-type well region and supplied with a reference voltage via a first wiring, and a second peripheral circuit on a region of the second P-type well region adjacent to the N-type well region and supplied with a reference voltage via a second wiring.