公开(公告)号：US20240014215A1

公开(公告)日：2024-01-11

申请号：US18343298

申请日：2023-06-28

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Alexandre Villaret ,  Olivier Weber ,  Franck Arnaud

IPC: H01L27/12 ,  H01L29/78 ,  H01L21/84

CPC classification number: H01L27/1207 ,  H01L29/7838 ,  H01L21/84

Abstract: A method can be used for manufacturing a high-voltage transistor in and on a high-voltage region of a silicon-on-insulator type bulk that includes a semiconductor film having a first thickness, electrically insulated from a carrier bulk by a buried dielectric layer. The semiconductor film in the high-voltage region is selectively epitaxially grown to a second thickness that is greater than the first thickness while the semiconductor film remains at the first thickness in a region outside the high-voltage region.