公开(公告)号：US11329067B2

公开(公告)日：2022-05-10

申请号：US16898700

申请日：2020-06-11

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Jean-Jacques Fagot ,  Philippe Boivin ,  Franck Arnaud

IPC: H01L27/12 ,  H01L21/762 ,  H01L29/808 ,  H01L21/84 ,  H01L27/06

Abstract: An electronic integrated circuit chip includes a first transistor arranged inside and on top of a solid substrate, a second transistor arranged inside and on top of a layer of semiconductor material on insulator having a first thickness, and a third transistor arranged inside and on top of a layer of semiconductor material on insulator having a second thickness. The second thickness is greater than the first thickness. The solid substrate extends underneath the layers of semiconductor material and is insulated from those layers by the insulator.

公开(公告)号：US20230387119A1

公开(公告)日：2023-11-30

申请号：US18324327

申请日：2023-05-26

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Olivier Weber ,  Franck Arnaud

IPC: H01L27/092 ,  H01L27/12 ,  H01L29/06 ,  H01L29/786 ,  H01L21/8238

CPC classification number: H01L27/0922 ,  H01L27/0928 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/78696 ,  H01L21/823807 ,  H01L21/823842 ,  H01L21/823892

Abstract: The semiconductor device of a silicon on insulator type includes a NMOS transistor in a P-type well of the carrier substrate, a PMOS transistor in an N-type well of the carrier substrate, and a power supply circuit configured to generate voltages in the P-type and N-type wells, so as to selectively provide neutral, forward and reverse back bias conditions to the NMOS transistor and the PMOS transistor. The neutral back bias condition is achieved when a first non-zero negative voltage is applied to the P-type well and a first non-zero positive voltage is applied to the N-type well. The NMOS and PMOS transistors are configured to have nominal threshold voltages in the neutral back bias condition.

公开(公告)号：US11653582B2

公开(公告)日：2023-05-16

申请号：US16184246

申请日：2018-11-08

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Franck Arnaud ,  David Galpin ,  Stephane Zoll ,  Olivier Hinsinger ,  Laurent Favennec ,  Jean-Pierre Oddou ,  Lucile Broussous ,  Philippe Boivin ,  Olivier Weber ,  Philippe Brun ,  Pierre Morin

IPC: H01L45/00 ,  H01L27/24 ,  G11C13/00

CPC classification number: H10N70/8616 ,  G11C13/0004 ,  G11C13/0069 ,  H10B63/30 ,  H10B63/80 ,  H10N70/011 ,  H10N70/021 ,  H10N70/231 ,  H10N70/826 ,  H10N70/8265 ,  H10N70/8413 ,  H10N70/882 ,  G11C2013/008

Abstract: An electronic chip includes memory cells made of a phase-change material and a transistor. First and second vias extend from the transistor through an intermediate insulating layer to a same height. A first metal level including a first interconnection track in contact with the first via is located over the intermediate insulating layer. A heating element for heating the phase-change material is located on the second via, and the phase-change material is located on the heating element. A second metal level including a second interconnection track is located above the phase-change material. A third via extends from the phase-change material to the second interconnection track.

公开(公告)号：US11690303B2

公开(公告)日：2023-06-27

申请号：US17216193

申请日：2021-03-29

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Remy Berthelon ,  Franck Arnaud

IPC: G11C11/00 ,  H10N70/20 ,  H10B63/00 ,  H10N70/00

CPC classification number: H10N70/231 ,  H10B63/00 ,  H10N70/021 ,  H10N70/063 ,  H10N70/8828

Abstract: An electronic chip includes at least a first array of first elementary cells and a second array of second elementary cells. The first and second elementary cells form two types of phase change memory having a storage element formed by a volume of phase change material having either a crystalline state or an amorphous state depending on the bit stored. Each first elementary cell includes a volume of a first phase change material, and each second elementary cell includes a volume of a second phase change material that is different from the first material. Each elementary cell includes a heating connector configured for the passage of a heating current adapted to cause a phase change of the volume of phase change material of the elementary cell.

公开(公告)号：US10714501B2

公开(公告)日：2020-07-14

申请号：US16057466

申请日：2018-08-07

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Crolles 2) SAS

Inventor： Jean-Jacques Fagot ,  Philippe Boivin ,  Franck Arnaud

IPC: H01L27/12 ,  H01L21/762 ,  H01L21/84 ,  H01L29/808 ,  H01L27/06

Abstract: An electronic integrated circuit chip includes a first transistor arranged inside and on top of a solid substrate, a second transistor arranged inside and on top of a layer of semiconductor material on insulator having a first thickness, and a third transistor arranged inside and on top of a layer of semiconductor material on insulator having a second thickness. The second thickness is greater than the first thickness. The solid substrate extends underneath the layers of semiconductor material and is insulated from those layers by the insulator.

公开(公告)号：US20180090389A1

公开(公告)日：2018-03-29

申请号：US15458109

申请日：2017-03-14

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Guillaume C. Ribes ,  Benjamin Dumont ,  Franck Arnaud

IPC: H01L21/8238 ,  H01L27/092 ,  H01L27/12 ,  H01L29/78 ,  H01L29/49 ,  H01L29/51 ,  H01L21/84

CPC classification number: H01L21/823842 ,  H01L21/82345 ,  H01L21/84 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/42372 ,  H01L29/42384 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66772 ,  H01L29/7833 ,  H01L29/7838

Abstract: An integrated circuit includes FDSOI-type MOS transistors formed inside and on top of a semiconductor layer resting on an insulating layer. The transistors include a logic MOS transistor of a first conductivity type, a logic MOS transistor of a second conductivity type, and an analog MOS transistor of the first conductivity type, A gate stack of the logic transistors successively includes a gate insulator layer, a first titanium nitride layer, a lanthanum layer, and a second titanium nitride layer. A gate stack of the analog transistor includes the gate insulator layer, the lanthanum layer and the second titanium nitride layer but not the first titanium nitride layer.

公开(公告)号：US12232435B2

公开(公告)日：2025-02-18

申请号：US18130184

申请日：2023-04-03

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Franck Arnaud ,  David Galpin ,  Stephane Zoll ,  Olivier Hinsinger ,  Laurent Favennec ,  Jean-Pierre Oddou ,  Lucile Broussous ,  Philippe Boivin ,  Olivier Weber ,  Philippe Brun ,  Pierre Morin

IPC: H10B63/00 ,  G11C13/00 ,  H10N70/00 ,  H10N70/20

Abstract: An integrated circuit includes a substrate with an active area, a first insulating layer, a second insulating layer, and a phase-change material. The integrated circuit further includes a heating element in an L-shape, with a long side in direct physical contact with the phase-change material and a short side in direct physical contact with a via. The heating element is surrounded by first, second, and third insulating spacers, with the first insulating spacer having a planar first sidewall in contact with the long side of the heating element, a convex second sidewall, and a planar bottom face in contact with the short side of the heating element. The second and third insulating spacers are in direct contact with the first insulating spacer and the long side of the heating element.

公开(公告)号：US12167703B2

公开(公告)日：2024-12-10

申请号：US18321347

申请日：2023-05-22

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Remy Berthelon ,  Franck Arnaud

IPC: G11C11/00 ,  H10B63/00 ,  H10N70/00 ,  H10N70/20

Abstract: An electronic chip includes at least a first array of first elementary cells and a second array of second elementary cells. The first and second elementary cells form two types of phase change memory having a storage element formed by a volume of phase change material having either a crystalline state or an amorphous state depending on the bit stored. Each first elementary cell includes a volume of a first phase change material, and each second elementary cell includes a volume of a second phase change material that is different from the first material. Each elementary cell includes a heating connector configured for the passage of a heating current adapted to cause a phase change of the volume of phase change material of the elementary cell.

公开(公告)号：US20240014215A1

公开(公告)日：2024-01-11

申请号：US18343298

申请日：2023-06-28

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Alexandre Villaret ,  Olivier Weber ,  Franck Arnaud

IPC: H01L27/12 ,  H01L29/78 ,  H01L21/84

CPC classification number: H01L27/1207 ,  H01L29/7838 ,  H01L21/84

Abstract: A method can be used for manufacturing a high-voltage transistor in and on a high-voltage region of a silicon-on-insulator type bulk that includes a semiconductor film having a first thickness, electrically insulated from a carrier bulk by a buried dielectric layer. The semiconductor film in the high-voltage region is selectively epitaxially grown to a second thickness that is greater than the first thickness while the semiconductor film remains at the first thickness in a region outside the high-voltage region.

公开(公告)号：US20170317106A1

公开(公告)日：2017-11-02

申请号：US15361937

申请日：2016-11-28

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Crolles 2) SAS

Inventor： Philippe Boivin ,  Franck Arnaud ,  Gregory Bidal ,  Dominique Golanski ,  Emmanuel Richard

IPC: H01L27/12 ,  H01L29/06 ,  H01L29/08 ,  H01L29/49

CPC classification number: H01L27/1207 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/4916

Abstract: An integrated circuit is formed using a substrate of a silicon-on-insulator type that includes a carrier substrate and a stack of a buried insulating layer and a semiconductor film on the carrier substrate. A first region without the stack separates a second region that includes the stack from a third region that also includes the stack. An MOS transistor has a gate dielectric region formed by a portion of the buried insulating layer in the second region and a gate region formed by a portion of the semiconductor film in the second region. The carrier substrate incorporates doped regions under the first region which form at least a part of a source region and drain region of the MOS transistor.