公开(公告)号：US20220028726A1

公开(公告)日：2022-01-27

申请号：US17376732

申请日：2021-07-15

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Denis MONNIER ,  Francois LEVERD

IPC: H01L21/762 ,  H01L27/146 ,  H01L21/02

Abstract: A method for forming a capacitive isolation trench in a semiconductor substrate includes digging a trench from a main surface of the substrate, the trench including an upper portion gradually widening from a neck in the direction of a lower portion of the trench. A coating of a first electrically isolating material is formed on the walls of the trench. A first semiconductor material is deposited on the coating, with the deposition being interrupted so as to leave a free space between the walls of the trench, the free space having an opening at the neck. A second electrically isolating material is deposited in the trench, with the deposition resulting in the formation of a plug closing the opening to form a closed cavity. The plug is etched so as to open the cavity, and a second semiconductor material or a metal is deposited so as to fill the cavity.