公开(公告)号：US20200211835A1

公开(公告)日：2020-07-02

申请号：US16709251

申请日：2019-12-10

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Delia RISTOIU ,  Pierre BAR ,  Francois LEVERD

IPC: H01L21/02 ,  H01L21/311

Abstract: The present disclosure relates to a method for forming a cavity that traverses a stack of layers including a bottom layer, a first portion of which locally presents an excess thickness, the method comprising a first step of non-selective etching and a second step of selective etching vertically in line with the first portion.

公开(公告)号：US20230005735A1

公开(公告)日：2023-01-05

申请号：US17940758

申请日：2022-09-08

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Delia RISTOIU ,  Pierre BAR ,  Francois LEVERD

IPC: H01L21/02 ,  H01L21/311

Abstract: The present disclosure relates to a method for forming a cavity that traverses a stack of layers including a bottom layer, a first portion of which locally presents an excess thickness, the method comprising a first step of non-selective etching and a second step of selective etching vertically in line with the first portion.

公开(公告)号：US20220028726A1

公开(公告)日：2022-01-27

申请号：US17376732

申请日：2021-07-15

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Denis MONNIER ,  Francois LEVERD

IPC: H01L21/762 ,  H01L27/146 ,  H01L21/02

Abstract: A method for forming a capacitive isolation trench in a semiconductor substrate includes digging a trench from a main surface of the substrate, the trench including an upper portion gradually widening from a neck in the direction of a lower portion of the trench. A coating of a first electrically isolating material is formed on the walls of the trench. A first semiconductor material is deposited on the coating, with the deposition being interrupted so as to leave a free space between the walls of the trench, the free space having an opening at the neck. A second electrically isolating material is deposited in the trench, with the deposition resulting in the formation of a plug closing the opening to form a closed cavity. The plug is etched so as to open the cavity, and a second semiconductor material or a metal is deposited so as to fill the cavity.

公开(公告)号：US20190214270A1

公开(公告)日：2019-07-11

申请号：US16240044

申请日：2019-01-04

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Pierre BAR ,  Francois LEVERD ,  Delia RISTOIU

IPC: H01L21/311 ,  H01L21/308 ,  H01L21/3065 ,  H01L21/02

CPC classification number: H01L21/31144 ,  G02B6/3636 ,  G02B6/3652 ,  G02B6/3692 ,  G02B6/42 ,  H01L21/02507 ,  H01L21/3065 ,  H01L21/3086 ,  H01L21/31116

Abstract: A cavity is etched in a stack of layers which includes a first layer made of a first material and a second layer made of a second material. To etch the cavity, a first etch mask having a first opening is formed over the stack of layer. The stack of layers is then etched through the first opening to a depth located in the second layer. A second mask having a second opening, the dimensions of which are smaller, in top view, than the first opening, is formed over the stack of layer. The second opening is located, in top view, opposite the area etched through the first opening. The second layer is then etched through the second opening to reach the first layer. The etch method used is configured to etch the second material selectively over the first material.