公开(公告)号：US10090827B2

公开(公告)日：2018-10-02

申请号：US15414419

申请日：2017-01-24

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Patrik Temleitner ,  Fady Abouzeid

IPC: H03K3/356 ,  H03K19/21

Abstract: A flip-flop includes a pulse-generator and a pulse-controlled latch. The pulse generator includes a first inverter to invert a clock signal, a second inverter to invert the inverted clock signal to generate a delayed clock signal, and a NOR gate having a first input coupled to an output of the first inverter, a second input coupled to the output of the second inverter, and an output, which, in operation, provides a pulse signal in response to a rising edge of a received clock signal. The pulse-controlled latch circuit has a data input and is controlled by the pulse signal and the delayed clock signal. The flip-flop may include a multiplexer to select an input signal.

公开(公告)号：US20180212596A1

公开(公告)日：2018-07-26

申请号：US15414419

申请日：2017-01-24

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Patrik Temleitner ,  Fady Abouzeid

IPC: H03K3/356 ,  H03K19/21

CPC classification number: H03K19/215 ,  H03K3/012 ,  H03K3/356173

Abstract: A flip-flop includes a pulse-generator and a pulse-controlled latch. The pulse generator includes a first inverter to invert a clock signal, a second inverter to invert the inverted clock signal to generate a delayed clock signal, and a NOR gate having a first input coupled to an output of the first inverter, a second input coupled to the output of the second inverter, and an output, which, in operation, provides a pulse signal in response to a rising edge of a received clock signal. The pulse-controlled latch circuit has a data input and is controlled by the pulse signal and the delayed clock signal. The flip-flop may include a multiplexer to select an input signal.