公开(公告)号：US20210111214A1

公开(公告)日：2021-04-15

申请号：US17128604

申请日：2020-12-21

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Francois ROY ,  Sonarith CHHUN

IPC: H01L27/146

Abstract: An electronic device includes a substrate semiconductor wafer with semiconductor portions separated from one another by through-passages. Electronic circuits and a dielectric layer with a network of electrical connections are formed at a front face of the substrate semiconductor wafer. Electrically conductive fillings are contained within the through-passages and are connected to the network of electrical connections. Interior dielectric layers for anti-diffusion protection are provided in the through-passages between the electrically conductive fillings and the semiconductor portions. Back side dielectric layers are joined to the interior dielectric layers.

公开(公告)号：US20210111215A1

公开(公告)日：2021-04-15

申请号：US17128608

申请日：2020-12-21

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Francois ROY ,  Sonarith CHHUN

IPC: H01L27/146

Abstract: An electronic device includes a substrate semiconductor wafer with semiconductor portions separated from one another by through-passages. Electronic circuits and a dielectric layer with a network of electrical connections are formed at a front face of the substrate semiconductor wafer. Electrically conductive fillings are contained within the through-passages and are connected to the network of electrical connections. Interior dielectric layers for anti-diffusion protection are provided in the through-passages between the electrically conductive fillings and the semiconductor portions. Back side dielectric layers are joined to the interior dielectric layers.

公开(公告)号：US20190189654A1

公开(公告)日：2019-06-20

申请号：US16285306

申请日：2019-02-26

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Sonarith CHHUN ,  Gregory IMBERT

IPC: H01L27/146 ,  H01L21/762 ,  H01L21/3065 ,  H01L27/12 ,  H01L27/06 ,  H01L21/84

CPC classification number: H01L27/1464 ,  H01L21/3065 ,  H01L21/76224 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/1203 ,  H01L27/1463 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/1469 ,  H01L2225/06541

Abstract: A semiconductor substrate has a back side surface and a front side surface. Metallization levels are provide at the front side surface. Capacitive deep trench isolation structures extend completely through the semiconductor substrate from the front side surface to the back side surface. Each capacitive deep trench isolation structure includes a conductive region insulated from the semiconductor substrate by an insulating liner. The conductive regions at first ends of the plurality of capacitive deep trench isolation structures are electrically connected to a first metallization level by electrical contacts. A bonding pad structure is located at the back side surface of the semiconductor substrate in direct physical and electrical connection to the conductive regions at second ends of the capacitive deep trench isolation structures.

公开(公告)号：US20190181176A1

公开(公告)日：2019-06-13

申请号：US16212790

申请日：2018-12-07

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Francois ROY ,  Sonarith CHHUN

IPC: H01L27/146

Abstract: An electronic device includes a substrate semiconductor wafer with semiconductor portions separated from one another by through-passages. Electronic circuits and a dielectric layer with a network of electrical connections are formed at a front face of the substrate semiconductor wafer. Electrically conductive fillings are contained within the through-passages and are connected to the network of electrical connections. Interior dielectric layers for anti-diffusion protection are provided in the through-passages between the electrically conductive fillings and the semiconductor portions. Back side dielectric layers are joined to the interior dielectric layers.