公开(公告)号：US20210318873A1

公开(公告)日：2021-10-14

申请号：US17211546

申请日：2021-03-24

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Gregory Trunde ,  Denis Dutey

IPC: G06F9/30 ,  G06F9/38 ,  G06F11/10

Abstract: In accordance with an embodiment, a method verifies contents of a plurality of registers having two first registers, where each of the plurality of registers is configured to store a data word and a verification bit. The method includes determining whether a value of the verification bit of each respective register of the plurality of registers corresponds to the data word of its respective register. The data words stored in the two first registers are selected so that the bits of a same rank of the two first registers include two complementary bits, each bit of a common binary word is associated with a respective register of the plurality of registers, and the value of the verification bit of each respective register depends on the data word of the respective register and the bit of the common binary word associated with the respective register.

公开(公告)号：US11797306B2

公开(公告)日：2023-10-24

申请号：US17660657

申请日：2022-04-26

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Gregory Trunde ,  Denis Dutey

IPC: G06F9/30 ,  G06F9/38 ,  G06F11/10

CPC classification number: G06F9/30101 ,  G06F9/30029 ,  G06F9/30105 ,  G06F9/384 ,  G06F11/10

Abstract: In accordance with an embodiment, a method verifies contents of a plurality of registers having two first registers, where each of the plurality of registers is configured to store a data word and a verification bit. The method includes determining whether a value of the verification bit of each respective register of the plurality of registers corresponds to the data word of its respective register. The data words stored in the two first registers are selected so that the bits of a same rank of the two first registers include two complementary bits, each bit of a common binary word is associated with a respective register of the plurality of registers, and the value of the verification bit of each respective register depends on the data word of the respective register and the bit of the common binary word associated with the respective register.

公开(公告)号：US20220253315A1

公开(公告)日：2022-08-11

申请号：US17660657

申请日：2022-04-26

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Gregory Trunde ,  Denis Dutey

IPC: G06F9/30 ,  G06F9/38 ,  G06F11/10

Abstract: In accordance with an embodiment, a method verifies contents of a plurality of registers having two first registers, where each of the plurality of registers is configured to store a data word and a verification bit. The method includes determining whether a value of the verification bit of each respective register of the plurality of registers corresponds to the data word of its respective register. The data words stored in the two first registers are selected so that the bits of a same rank of the two first registers include two complementary bits, each bit of a common binary word is associated with a respective register of the plurality of registers, and the value of the verification bit of each respective register depends on the data word of the respective register and the bit of the common binary word associated with the respective register.

公开(公告)号：US11314513B2

公开(公告)日：2022-04-26

申请号：US17211546

申请日：2021-03-24

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Gregory Trunde ,  Denis Dutey

IPC: G06F9/30 ,  G06F9/38 ,  G06F11/10

Abstract: In accordance with an embodiment, a method verifies contents of a plurality of registers having two first registers, where each of the plurality of registers is configured to store a data word and a verification bit. The method includes determining whether a value of the verification bit of each respective register of the plurality of registers corresponds to the data word of its respective register. The data words stored in the two first registers are selected so that the bits of a same rank of the two first registers include two complementary bits, each bit of a common binary word is associated with a respective register of the plurality of registers, and the value of the verification bit of each respective register depends on the data word of the respective register and the bit of the common binary word associated with the respective register.