-
公开(公告)号：US11797306B2
公开(公告)日：2023-10-24
申请号：US17660657
申请日：2022-04-26
Applicant: STMicroelectronics (Grenoble 2) SAS
Inventor： Gregory Trunde , Denis Dutey
CPC classification number: G06F9/30101 , G06F9/30029 , G06F9/30105 , G06F9/384 , G06F11/10
Abstract: In accordance with an embodiment, a method verifies contents of a plurality of registers having two first registers, where each of the plurality of registers is configured to store a data word and a verification bit. The method includes determining whether a value of the verification bit of each respective register of the plurality of registers corresponds to the data word of its respective register. The data words stored in the two first registers are selected so that the bits of a same rank of the two first registers include two complementary bits, each bit of a common binary word is associated with a respective register of the plurality of registers, and the value of the verification bit of each respective register depends on the data word of the respective register and the bit of the common binary word associated with the respective register.
-
公开(公告)号：US11416022B2
公开(公告)日：2022-08-16
申请号：US16879535
申请日：2020-05-20
Applicant: STMicroelectronics (Grenoble 2) SAS
Inventor： Stephane Martin , Denis Dutey
IPC: G06J1/02 , G06F1/14 , G06F1/08 , H04L7/02 , G01R31/317
Abstract: In an embodiment a device includes a first circuit configured to send a signal comprising numbers successively separated by a constant value to at least one second circuit, each second circuit being in a clock domain different from a clock domain of the first circuit and at least one third circuit configured to determine whether the successive numbers of the signal received by the second circuit are separated by the constant value, wherein the signal is sent to a respective third circuit in each of the clock domains different from the clock domain of the first circuit.
-
公开(公告)号：US20200379924A1
公开(公告)日：2020-12-03
申请号：US16881949
申请日：2020-05-22
Applicant: STMicroelectronics (Grenoble 2) SAS , STMicroelectronics International N.V. , STMicroelectronics S.r.l.
Inventor： Riccardo Gemelli , Denis Dutey , Om Ranjan
Abstract: A method is provided to access a data storage memory that stores data signals in a plurality of indexed memory locations. An access control circuit receives a memory access request signals from a processing circuit. The method includes replicating the respective memory access request signals to provide for each a respective replicated memory access request signal, accessing indexed internal memory locations to retrieve a first data signal retrieved as a function of the respective memory access request signal and a second data signal retrieved as a function of the respective replicated memory access request signal, and checking for identity the first data signal and the at least one second data signal. The access control circuit transmits to the processing circuit a data signal or an integrity error flag signal as a result of the identity check.
-
公开(公告)号：US11436162B2
公开(公告)日：2022-09-06
申请号：US16881949
申请日：2020-05-22
Applicant: STMicroelectronics (Grenoble 2) SAS , STMicroelectronics International N.V. , STMicroelectronics S.r.l.
Inventor： Riccardo Gemelli , Denis Dutey , Om Ranjan
Abstract: A method is provided to access a data storage memory that stores data signals in a plurality of indexed memory locations. An access control circuit receives a memory access request signals from a processing circuit. The method includes replicating the respective memory access request signals to provide for each a respective replicated memory access request signal, accessing indexed internal memory locations to retrieve a first data signal retrieved as a function of the respective memory access request signal and a second data signal retrieved as a function of the respective replicated memory access request signal, and checking for identity the first data signal and the at least one second data signal. The access control circuit transmits to the processing circuit a data signal or an integrity error flag signal as a result of the identity check.
-
Patent Agency Ranking
公开(公告)号：US20200379506A1
公开(公告)日：2020-12-03
申请号：US16879535
申请日：2020-05-20
Applicant: STMicroelectronics (Grenoble 2) SAS
Inventor： Stephane Martin , Denis Dutey
Abstract: In an embodiment a device includes a first circuit configured to send a signal comprising numbers successively separated by a constant value to at least one second circuit, each second circuit being in a clock domain different from a clock domain of the first circuit and at least one third circuit configured to determine whether the successive numbers of the signal received by the second circuit are separated by the constant value, wherein the signal is sent to a respective third circuit in each of the clock domains different from the clock domain of the first circuit.
-
公开(公告)号：US20210318873A1
公开(公告)日：2021-10-14
申请号：US17211546
申请日：2021-03-24
Applicant: STMicroelectronics (Grenoble 2) SAS
Inventor： Gregory Trunde , Denis Dutey
Abstract: In accordance with an embodiment, a method verifies contents of a plurality of registers having two first registers, where each of the plurality of registers is configured to store a data word and a verification bit. The method includes determining whether a value of the verification bit of each respective register of the plurality of registers corresponds to the data word of its respective register. The data words stored in the two first registers are selected so that the bits of a same rank of the two first registers include two complementary bits, each bit of a common binary word is associated with a respective register of the plurality of registers, and the value of the verification bit of each respective register depends on the data word of the respective register and the bit of the common binary word associated with the respective register.
-
公开(公告)号：US20220253315A1
公开(公告)日：2022-08-11
申请号：US17660657
申请日：2022-04-26
Applicant: STMicroelectronics (Grenoble 2) SAS
Inventor： Gregory Trunde , Denis Dutey
Abstract: In accordance with an embodiment, a method verifies contents of a plurality of registers having two first registers, where each of the plurality of registers is configured to store a data word and a verification bit. The method includes determining whether a value of the verification bit of each respective register of the plurality of registers corresponds to the data word of its respective register. The data words stored in the two first registers are selected so that the bits of a same rank of the two first registers include two complementary bits, each bit of a common binary word is associated with a respective register of the plurality of registers, and the value of the verification bit of each respective register depends on the data word of the respective register and the bit of the common binary word associated with the respective register.
-
公开(公告)号：US11314513B2
公开(公告)日：2022-04-26
申请号：US17211546
申请日：2021-03-24
Applicant: STMicroelectronics (Grenoble 2) SAS
Inventor： Gregory Trunde , Denis Dutey
Abstract: In accordance with an embodiment, a method verifies contents of a plurality of registers having two first registers, where each of the plurality of registers is configured to store a data word and a verification bit. The method includes determining whether a value of the verification bit of each respective register of the plurality of registers corresponds to the data word of its respective register. The data words stored in the two first registers are selected so that the bits of a same rank of the two first registers include two complementary bits, each bit of a common binary word is associated with a respective register of the plurality of registers, and the value of the verification bit of each respective register depends on the data word of the respective register and the bit of the common binary word associated with the respective register.
-
公开(公告)号：US11055173B2
公开(公告)日：2021-07-06
申请号：US16703672
申请日：2019-12-04
Applicant: STMicroelectronics (Grenoble 2) SAS , STMicroelectronics International N.V. , STMicroelectronics S.r.l.
Inventor： Om Ranjan , Riccardo Gemelli , Denis Dutey
Abstract: Application data and error correction code (ECC) checkbits associated with that application data are stored in a first memory. The ECC checkbits, but not the application data, are stored in a second memory. In response to a request to read the application data from the first memory, the ECC checkbits from the first memory are also read and used to detect, and possibly correct, errors in the read application data. The ECC checkbits are further output from both the first and second memories for bit-by-bit comparison. In response to a failure of the bit-by-bit comparison, a signal indicating possible malfunction of one or the other or both of the first and second memories is generated.
-
-
-
-
-
-
-
-
Search Results
9
records
(took 0.012 seconds)
